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* Update testsMiodrag Milanovic2023-03-207-16/+16
* fabulous: Add support for mapping carry chainsgatecat2023-02-271-0/+9
* Genericising bug1836.ysKrystalDelusion2023-02-211-20/+12
* bug3205.ys removedKrystalDelusion2023-02-211-57/+0
* Removing extra `default_nettype` linesKrystalDelusion2023-02-211-2/+0
* Fix for sync_ram_sdp not being final moduleKrystalDelusion2023-02-211-1/+1
* Tests for ram_style = "huge"KrystalDelusion2023-02-214-0/+219
* Testing TDP synth mappingKrystalDelusion2023-02-213-0/+49
* Asymmetric port ram tests with XilinxKrystalDelusion2023-02-213-0/+193
* Addings tests for #1836 and #3205KrystalDelusion2023-02-213-0/+120
* fabulous: Allow adding extra custom prims and map rulesgatecat2022-11-173-0/+21
* fabulous: improvements to the passgatecat2022-11-177-0/+141
* Reenable existing equiv_opt testsJannis Harder2022-10-072-3/+3
* Fix tests for check in equiv_optJannis Harder2022-10-075-7/+17
* support file locations containing spacesMiodrag Milanovic2022-08-081-0/+1
* gatemate: Add test for LUT tree mappinggatecat2022-06-273-0/+813
* efinix: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-12/+1
* ice40: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-56/+0
* xilinx: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-183-46/+15
* nexus: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-2/+2
* ecp5: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-135/+18
* intel_alm: M10K write-enable is negative-trueLofty2022-03-091-1/+2
* gowin: Fix LUT RAM inference, add more models.Marcelina Kościelnicka2022-02-091-3/+2
* anlogic: support BRAM mappingIcenowy Zheng2021-12-172-1/+14
* Fix the tests we just brokeClaire Xenia Wolf2021-12-101-2/+2
* Add gitignore for gatemateMiodrag Milanovic2021-12-031-0/+4
* synth_gatemate: Update passPatrick Urban2021-11-131-4/+8
* synth_gatemate: Apply new test practice with assert-maxPatrick Urban2021-11-137-12/+12
* synth_gatemate: Fix fsm testPatrick Urban2021-11-131-2/+2
* Allow initial blocks to be disabled during testsPatrick Urban2021-11-136-4/+20
* synth_gatemate: Initial implementationPatrick Urban2021-11-1314-0/+337
* iopadmap: Add native support for negative-polarity output enable.Marcelina Kościelnicka2021-11-092-3/+3
* FfData: some refactoring.Marcelina Kościelnicka2021-10-071-2/+3
* abc9: replace cell type/parameters if derived type already processed (#2991)Eddie Hung2021-09-091-0/+7
* Gowin: deal with active-low tristate (#2971)Pepijn de Vos2021-08-201-1/+2
* test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.Marcelina Kościelnicka2021-08-112-78/+156
* Add v2 memory cells.Marcelina Kościelnicka2021-08-112-25/+25
* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-291-0/+24
* Fix files with CRLF line endingsClaire Xenia Wolf2021-06-093-73/+73
* memory_bram: Reuse extract_rdff helper for make_outreg.Marcelina Kościelnicka2021-05-254-17/+14
* intel_alm: Fix illegal carry chainsgatecat2021-05-152-4/+4
* intel_alm: Add global buffer insertiongatecat2021-05-1513-41/+41
* intel_alm: Add IO buffer insertiongatecat2021-05-1513-39/+39
* Add default assignments to SB_LUT4Claire Xenia Wolf2021-04-201-1/+1
* quicklogic: ABC9 synthesisLofty2021-04-176-17/+17
* quicklogic: Add .gitignore file for test outputs.Marcelina Kościelnicka2021-03-231-0/+4
* quicklogic: PolarPro 3 supportLofty2021-03-1810-0/+262
* ast: Use better parameter serialization for paramod names.Marcelina Kościelnicka2021-03-181-3/+3
* Blackbox all whiteboxes after synthesisgatecat2021-03-171-9/+9
* machxo2: Switch to LUT4 sim model which propagates less undefined/don't care ...William D. Jones2021-02-231-1/+1
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