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* support file locations containing spacesMiodrag Milanovic2022-08-081-0/+1
* gatemate: Add test for LUT tree mappinggatecat2022-06-273-0/+813
* efinix: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-12/+1
* ice40: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-56/+0
* xilinx: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-183-46/+15
* nexus: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-2/+2
* ecp5: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-135/+18
* intel_alm: M10K write-enable is negative-trueLofty2022-03-091-1/+2
* gowin: Fix LUT RAM inference, add more models.Marcelina Kościelnicka2022-02-091-3/+2
* anlogic: support BRAM mappingIcenowy Zheng2021-12-172-1/+14
* Fix the tests we just brokeClaire Xenia Wolf2021-12-101-2/+2
* Add gitignore for gatemateMiodrag Milanovic2021-12-031-0/+4
* synth_gatemate: Update passPatrick Urban2021-11-131-4/+8
* synth_gatemate: Apply new test practice with assert-maxPatrick Urban2021-11-137-12/+12
* synth_gatemate: Fix fsm testPatrick Urban2021-11-131-2/+2
* Allow initial blocks to be disabled during testsPatrick Urban2021-11-136-4/+20
* synth_gatemate: Initial implementationPatrick Urban2021-11-1314-0/+337
* iopadmap: Add native support for negative-polarity output enable.Marcelina Kościelnicka2021-11-092-3/+3
* FfData: some refactoring.Marcelina Kościelnicka2021-10-071-2/+3
* abc9: replace cell type/parameters if derived type already processed (#2991)Eddie Hung2021-09-091-0/+7
* Gowin: deal with active-low tristate (#2971)Pepijn de Vos2021-08-201-1/+2
* test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.Marcelina Kościelnicka2021-08-112-78/+156
* Add v2 memory cells.Marcelina Kościelnicka2021-08-112-25/+25
* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-291-0/+24
* Fix files with CRLF line endingsClaire Xenia Wolf2021-06-093-73/+73
* memory_bram: Reuse extract_rdff helper for make_outreg.Marcelina Kościelnicka2021-05-254-17/+14
* intel_alm: Fix illegal carry chainsgatecat2021-05-152-4/+4
* intel_alm: Add global buffer insertiongatecat2021-05-1513-41/+41
* intel_alm: Add IO buffer insertiongatecat2021-05-1513-39/+39
* Add default assignments to SB_LUT4Claire Xenia Wolf2021-04-201-1/+1
* quicklogic: ABC9 synthesisLofty2021-04-176-17/+17
* quicklogic: Add .gitignore file for test outputs.Marcelina Kościelnicka2021-03-231-0/+4
* quicklogic: PolarPro 3 supportLofty2021-03-1810-0/+262
* ast: Use better parameter serialization for paramod names.Marcelina Kościelnicka2021-03-181-3/+3
* Blackbox all whiteboxes after synthesisgatecat2021-03-171-9/+9
* machxo2: Switch to LUT4 sim model which propagates less undefined/don't care ...William D. Jones2021-02-231-1/+1
* machxo2: Update tribuf test to reflect active-low OE.William D. Jones2021-02-231-1/+2
* machxo2: Add believed-to-be-correct tribuf test.William D. Jones2021-02-231-0/+9
* machxo2: Add passing fsm, mux, and shifter tests.William D. Jones2021-02-233-0/+65
* machxo2: Add add_sub test. Fix tests to include FACADE_IO primitives.William D. Jones2021-02-233-3/+11
* machxo2: Add dffe test.William D. Jones2021-02-231-0/+9
* machxo2: Add dff.ys test, fix another cells_map.v typo.William D. Jones2021-02-231-0/+10
* machxo2: Add test/arch/machxo2 directory (test does not pass).William D. Jones2021-02-233-0/+14
* xilinx_dffopt: Don't crash on missing IS_*_INVERTED.Marcelina Kościelnicka2021-01-272-1/+48
* nexus: DSP inference supportDavid Shah2020-11-201-12/+34
* Update nexus arch tests to new harnessXiretza2020-10-291-19/+3
* xilinx: Fix attributes_test.ysMarcelina Kościelnicka2020-10-241-4/+2
* memory_dff: Fix needlessly duplicating enable bits.Marcelina Kościelnicka2020-10-221-0/+24
* Merge pull request #2397 from daveshah1/nexusMiodrag Milanović2020-10-1915-0/+298
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| * synth_nexus: Initial implementationDavid Shah2020-10-1515-0/+298
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