| Commit message (Expand) | Author | Age | Files | Lines |
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| * | gowin: Fix LUT RAM inference, add more models. | Marcelina Kościelnicka | 2022-02-09 | 1 | -3/+2 |
| * | anlogic: support BRAM mapping | Icenowy Zheng | 2021-12-17 | 2 | -1/+14 |
| * | Fix the tests we just broke | Claire Xenia Wolf | 2021-12-10 | 1 | -2/+2 |
| * | Add gitignore for gatemate | Miodrag Milanovic | 2021-12-03 | 1 | -0/+4 |
| * | synth_gatemate: Update pass | Patrick Urban | 2021-11-13 | 1 | -4/+8 |
| * | synth_gatemate: Apply new test practice with assert-max | Patrick Urban | 2021-11-13 | 7 | -12/+12 |
| * | synth_gatemate: Fix fsm test | Patrick Urban | 2021-11-13 | 1 | -2/+2 |
| * | Allow initial blocks to be disabled during tests | Patrick Urban | 2021-11-13 | 6 | -4/+20 |
| * | synth_gatemate: Initial implementation | Patrick Urban | 2021-11-13 | 14 | -0/+337 |
| * | iopadmap: Add native support for negative-polarity output enable. | Marcelina Kościelnicka | 2021-11-09 | 2 | -3/+3 |
| * | FfData: some refactoring. | Marcelina Kościelnicka | 2021-10-07 | 1 | -2/+3 |
| * | abc9: replace cell type/parameters if derived type already processed (#2991) | Eddie Hung | 2021-09-09 | 1 | -0/+7 |
| * | Gowin: deal with active-low tristate (#2971) | Pepijn de Vos | 2021-08-20 | 1 | -1/+2 |
| * | test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer. | Marcelina Kościelnicka | 2021-08-11 | 2 | -78/+156 |
| * | Add v2 memory cells. | Marcelina Kościelnicka | 2021-08-11 | 2 | -25/+25 |
| * | opt_lut: Allow more than one -dlogic per cell type. | Marcelina Kościelnicka | 2021-07-29 | 1 | -0/+24 |
| * | Fix files with CRLF line endings | Claire Xenia Wolf | 2021-06-09 | 3 | -73/+73 |
| * | memory_bram: Reuse extract_rdff helper for make_outreg. | Marcelina Kościelnicka | 2021-05-25 | 4 | -17/+14 |
| * | intel_alm: Fix illegal carry chains | gatecat | 2021-05-15 | 2 | -4/+4 |
| * | intel_alm: Add global buffer insertion | gatecat | 2021-05-15 | 13 | -41/+41 |
| * | intel_alm: Add IO buffer insertion | gatecat | 2021-05-15 | 13 | -39/+39 |
| * | Add default assignments to SB_LUT4 | Claire Xenia Wolf | 2021-04-20 | 1 | -1/+1 |
| * | quicklogic: ABC9 synthesis | Lofty | 2021-04-17 | 6 | -17/+17 |
| * | quicklogic: Add .gitignore file for test outputs. | Marcelina Kościelnicka | 2021-03-23 | 1 | -0/+4 |
| * | quicklogic: PolarPro 3 support | Lofty | 2021-03-18 | 10 | -0/+262 |
| * | ast: Use better parameter serialization for paramod names. | Marcelina Kościelnicka | 2021-03-18 | 1 | -3/+3 |
| * | Blackbox all whiteboxes after synthesis | gatecat | 2021-03-17 | 1 | -9/+9 |
| * | machxo2: Switch to LUT4 sim model which propagates less undefined/don't care ... | William D. Jones | 2021-02-23 | 1 | -1/+1 |
| * | machxo2: Update tribuf test to reflect active-low OE. | William D. Jones | 2021-02-23 | 1 | -1/+2 |
| * | machxo2: Add believed-to-be-correct tribuf test. | William D. Jones | 2021-02-23 | 1 | -0/+9 |
| * | machxo2: Add passing fsm, mux, and shifter tests. | William D. Jones | 2021-02-23 | 3 | -0/+65 |
| * | machxo2: Add add_sub test. Fix tests to include FACADE_IO primitives. | William D. Jones | 2021-02-23 | 3 | -3/+11 |
| * | machxo2: Add dffe test. | William D. Jones | 2021-02-23 | 1 | -0/+9 |
| * | machxo2: Add dff.ys test, fix another cells_map.v typo. | William D. Jones | 2021-02-23 | 1 | -0/+10 |
| * | machxo2: Add test/arch/machxo2 directory (test does not pass). | William D. Jones | 2021-02-23 | 3 | -0/+14 |
| * | xilinx_dffopt: Don't crash on missing IS_*_INVERTED. | Marcelina Kościelnicka | 2021-01-27 | 2 | -1/+48 |
| * | nexus: DSP inference support | David Shah | 2020-11-20 | 1 | -12/+34 |
| * | Update nexus arch tests to new harness | Xiretza | 2020-10-29 | 1 | -19/+3 |
| * | xilinx: Fix attributes_test.ys | Marcelina Kościelnicka | 2020-10-24 | 1 | -4/+2 |
| * | memory_dff: Fix needlessly duplicating enable bits. | Marcelina Kościelnicka | 2020-10-22 | 1 | -0/+24 |
| * | Merge pull request #2397 from daveshah1/nexus | Miodrag Milanović | 2020-10-19 | 15 | -0/+298 |
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| | * | synth_nexus: Initial implementation | David Shah | 2020-10-15 | 15 | -0/+298 |
| * | | Merge pull request #2380 from Xiretza/parallel-tests | clairexen | 2020-10-01 | 7 | -133/+21 |
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| | * | tests: Centralize test collection and Makefile generation | Xiretza | 2020-09-21 | 7 | -133/+21 |
| * | | xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325) | Eddie Hung | 2020-09-23 | 1 | -0/+37 |
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| * | intel_alm: Add multiply signedness to cells | Dan Ravensloft | 2020-08-26 | 2 | -6/+44 |
| * | techmap/shift_shiftx: Remove the "shiftx2mux" special path. | Marcelina Kościelnicka | 2020-08-20 | 1 | -2/+3 |
| * | Replace opt_rmdff with opt_dff. | Marcelina Kościelnicka | 2020-08-07 | 7 | -31/+28 |
| * | opt_expr: Remove -clkinv option, make it the default. | Marcelina Kościelnicka | 2020-07-31 | 1 | -2/+1 |
| * | synth_ice40: Use opt_dff. | Marcelina Kościelnicka | 2020-07-30 | 1 | -1/+1 |
