| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | add tristate buffer and test | Pepijn de Vos | 2019-10-28 | 1 | -0/+13 |
| * | do not use wide luts in testcase | Pepijn de Vos | 2019-10-28 | 1 | -3/+3 |
| * | ALU sim tweaks | Pepijn de Vos | 2019-10-24 | 1 | -2/+2 |
| * | Add some tests | Pepijn de Vos | 2019-10-21 | 10 | -0/+224 |
| * | fixed error | Miodrag Milanovic | 2019-10-18 | 1 | -1/+1 |
| * | Unify verilog style | Miodrag Milanovic | 2019-10-18 | 11 | -191/+157 |
| * | Common memory test now shared | Miodrag Milanovic | 2019-10-18 | 10 | -89/+5 |
| * | Remove not needed tests | Miodrag Milanovic | 2019-10-18 | 4 | -52/+0 |
| * | Share common tests | Miodrag Milanovic | 2019-10-18 | 103 | -1316/+178 |
| * | fix yosys path | Miodrag Milanovic | 2019-10-18 | 1 | -2/+2 |
| * | Fix path to yosys | Miodrag Milanovic | 2019-10-18 | 5 | -5/+5 |
| * | Moved all tests in arch sub directory | Miodrag Milanovic | 2019-10-18 | 150 | -0/+3548 |
| * | Add simcells.v, simlib.v, and some output | Eddie Hung | 2019-06-27 | 1 | -1/+11 |
| * | tests: Check that Icarus can parse arch sim models | David Shah | 2019-06-26 | 1 | -0/+8 |
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index : iCE40/yosys | |
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