| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | ice40: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 1 | -56/+0 |
| * | test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer. | Marcelina Kościelnicka | 2021-08-11 | 1 | -27/+54 |
| * | Add v2 memory cells. | Marcelina Kościelnicka | 2021-08-11 | 1 | -8/+8 |
| * | tests: remove write_ilang | Eddie Hung | 2020-04-20 | 1 | -1/+0 |
| * | ice40: do not map FFRAM if explicitly requested otherwise. | whitequark | 2020-04-03 | 1 | -8/+28 |
| * | ecp5: add support for both 1364.1 and LSE RAM/ROM attributes. | whitequark | 2020-02-06 | 1 | -0/+16 |
| * | ice40: match memory inference attribute values case insensitive. | whitequark | 2020-02-06 | 1 | -0/+6 |
| * | ice40: add support for both 1364.1 and LSE RAM/ROM attributes. | whitequark | 2020-02-06 | 1 | -0/+126 |
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index : iCE40/yosys | |
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