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* Added $assert cellClifford Wolf2014-01-191-0/+15
* Fixed $lut simlib model for a wider range of toolsClifford Wolf2014-01-181-10/+12
* More changes to simlib to make it friendlier to a wider range of toolsClifford Wolf2014-01-181-10/+14
* Fixed a type in $mem model in simlib.vClifford Wolf2014-01-181-1/+1
* Removed cases of trailing comma in stdcells.vClifford Wolf2014-01-181-3/+3
* Added $bu0 cell to simlib.vClifford Wolf2014-01-181-0/+22
* Added techlibs/common/pmux2mux.vClifford Wolf2014-01-172-1/+26
* Various small cleanups in stdcells.v techmap codeClifford Wolf2013-12-311-68/+38
* Added $bu0 cell (for easy correct $eq/$ne mapping)Clifford Wolf2013-12-281-4/+10
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-272-0/+86
* Using simplemap mappers from techmapClifford Wolf2013-11-241-714/+40
* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-244-20/+23
* Added "techmap -share_map" optionClifford Wolf2013-11-241-4/+4
* Fixed xilinx/example_sim_counter test benchClifford Wolf2013-11-241-1/+1
* Added more generic _TECHMAP_ wire mechanism to techmap passClifford Wolf2013-11-231-1/+1
* Updated abcClifford Wolf2013-11-212-0/+11
* Install simlib in datdirClifford Wolf2013-11-191-0/+6
* Added commented-out osu025 maping commands to cmos techmap exampleClifford Wolf2013-11-181-0/+5
* Cleanups and bugfixes in response to new internal cell checkerClifford Wolf2013-11-112-47/+43
* Fixed techmap of $reduce_xnor with multi-bit outputsClifford Wolf2013-11-071-1/+7
* Fixed techmap of $gt and $ge with multi-bit outputsClifford Wolf2013-11-061-2/+14
* Improved width extension with regard to undef propagationClifford Wolf2013-11-061-11/+11
* Added DFFSR cell to techlibs/cmos/cmos_cells.libClifford Wolf2013-10-312-0/+26
* [EXAMPLES] Ported the mojo counter example to Zynq ZED board.James Walmsley2013-10-274-0/+56
* Cleanups in xilinx examplesClifford Wolf2013-10-273-144/+28
* Added synth_xilinx commandClifford Wolf2013-10-272-0/+219
* Moved simple xilinx counter sim example to subdirClifford Wolf2013-10-273-0/+0
* Xilinx mojo_counter example is now workingClifford Wolf2013-10-273-4/+9
* Renamed techlibs/xilinx7 to techlibs/xilinxClifford Wolf2013-10-268-0/+0
* Improved xilinx mojo_counter exampleClifford Wolf2013-10-262-2/+5
* Added another xilinx example (not funcional yet)Clifford Wolf2013-10-264-0/+101
* Bugfix in dffsr techmap rulesClifford Wolf2013-10-181-8/+8
* Added techmap rules for $sr, $dffsr and $dlatchClifford Wolf2013-10-181-0/+181
* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-181-0/+166
* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-181-20/+76
* Added map, par and bitgen to xlinx7 exampleClifford Wolf2013-10-161-2/+39
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-156-7/+7
* Added spice testbench to techlibs/cmosClifford Wolf2013-09-144-3/+73
* Added spice backendClifford Wolf2013-09-144-0/+78
* Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)Clifford Wolf2013-08-271-2/+10
* Added simple xilinx7 technology mapping filesClifford Wolf2013-08-224-0/+167
* Implemented same div-by-zero behavior as found in other synthesis toolsClifford Wolf2013-08-151-2/+31
* Added $div and $mod technology mappingClifford Wolf2013-08-091-9/+93
* Added $lut cells and abc lut mapping supportClifford Wolf2013-07-231-0/+32
* Fixed shift ops with large right hand sideClifford Wolf2013-07-091-6/+6
* More fixes for bugs found using xsthammerClifford Wolf2013-06-131-8/+7
* More sign-extension related fixesClifford Wolf2013-06-101-12/+13
* Implemented technology mapping for multipliers (using array multiplier)Clifford Wolf2013-06-031-4/+30
* Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.vClifford Wolf2013-04-071-4/+4
* Added EXTRA_TARGETS Makefile variableClifford Wolf2013-03-281-1/+1
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