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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-06 22:59:45 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-06 22:59:45 +0100 |
| commit | b41740060b28039c7e01fede41e6affb91867e02 (patch) | |
| tree | 70423eda7b4254b17ec5f9770afc29a92b1d37fe /techlibs | |
| parent | f485962c5e0866d84e56c7c95ded2cb9c5cba190 (diff) | |
| download | yosys-b41740060b28039c7e01fede41e6affb91867e02.tar.gz yosys-b41740060b28039c7e01fede41e6affb91867e02.tar.bz2 yosys-b41740060b28039c7e01fede41e6affb91867e02.zip | |
Fixed techmap of $gt and $ge with multi-bit outputs
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/stdcells.v | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/techlibs/common/stdcells.v b/techlibs/common/stdcells.v index d89b39b8a..ca73f5bcd 100644 --- a/techlibs/common/stdcells.v +++ b/techlibs/common/stdcells.v @@ -855,9 +855,15 @@ output [Y_WIDTH-1:0] Y; ) ge_via_le ( .A(B), .B(A), - .Y(Y) + .Y(Y[0]) ); +generate + if (Y_WIDTH > 1) begin:V + assign Y[Y_WIDTH-1:1] = 0; + end +endgenerate + endmodule // -------------------------------------------------------- @@ -882,9 +888,15 @@ output [Y_WIDTH-1:0] Y; ) gt_via_lt ( .A(B), .B(A), - .Y(Y) + .Y(Y[0]) ); +generate + if (Y_WIDTH > 1) begin:V + assign Y[Y_WIDTH-1:1] = 0; + end +endgenerate + endmodule // -------------------------------------------------------- |