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* Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-106-32/+150
* Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-105-20/+14
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| * substr() -> compare()Eddie Hung2019-08-071-3/+3
| * RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-1/+1
| * Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-072-117/+252
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| * | stoi -> atoiEddie Hung2019-08-073-3/+3
| * | Fix spacingEddie Hung2019-08-061-3/+3
| * | Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-061-1/+1
| * | Make liberal use of IdString.in()Eddie Hung2019-08-061-14/+8
* | | Merge pull request #1270 from YosysHQ/eddie/alu_lcu_docClifford Wolf2019-08-101-8/+36
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| * | | Reformat so it shows up/looks nice when "help $alu" and "help $alu+"Eddie Hung2019-08-091-25/+34
| * | | A bit more on where $lcu comes fromEddie Hung2019-08-091-0/+2
| * | | Add more commentsEddie Hung2019-08-091-4/+18
| * | | Add a few comments to document $alu and $lcuEddie Hung2019-08-081-9/+12
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* | | Allow whitebox modules to be overwrittenEddie Hung2019-08-071-2/+0
* | | Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPEREddie Hung2019-08-073-10/+17
* | | Add testEddie Hung2019-08-071-1/+10
* | | Remove ice40_unlutEddie Hung2019-08-072-107/+0
* | | Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDEREddie Hung2019-08-073-39/+14
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* | Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixesDavid Shah2019-08-071-101/+244
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| * | ecp5: Make cells_sim.v consistent with nextpnrDavid Shah2019-08-071-101/+244
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* | Merge pull request #1249 from mmicko/anlogic_fixClifford Wolf2019-08-071-16/+8
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| * anlogic : Fix alu mappingMiodrag Milanovic2019-08-031-16/+8
* | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-0/+19
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* Merge pull request #1239 from mmicko/mingw_fixClifford Wolf2019-08-023-6/+6
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| * Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-013-6/+6
* | RST -> RSTBRST for RAMB8BWEREddie Hung2019-07-291-3/+3
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* Merge branch 'ZirconiumX-synth_intel_m9k'Clifford Wolf2019-07-254-5/+11
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| * intel: Map M9K BRAM only on families that have itDan Ravensloft2019-07-234-5/+12
* | Merge pull request #1218 from ZirconiumX/synth_intel_iopadsClifford Wolf2019-07-251-8/+8
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| * | intel: Make -noiopads the defaultDan Ravensloft2019-07-241-8/+8
* | | Merge pull request #1224 from YosysHQ/xilinx_fix_ffEddie Hung2019-07-251-2/+2
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| * | xilinx: Fix missing cell name underscore in cells_map.vDavid Shah2019-07-251-2/+2
* | | ice40: Fix test_dsp_model.shDavid Shah2019-07-191-1/+1
* | | ice40/cells_sim.v: Fix sign of J and K partial productsDavid Shah2019-07-191-5/+7
* | | ice40/cells_sim.v: LSB of A/B only signed in 8x8 modeDavid Shah2019-07-191-2/+2
* | | Add tests for all combinations of A and B signedness for comb mulEddie Hung2019-07-192-1/+229
* | | Don't copy ref if exists alreadyEddie Hung2019-07-191-1/+3
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* | Merge pull request #1208 from ZirconiumX/intel_cleanupsDavid Shah2019-07-181-29/+14
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| * | synth_intel: Use stringfDan Ravensloft2019-07-181-7/+2
| * | synth_intel: s/not family/no family/Dan Ravensloft2019-07-181-2/+2
| * | intel_synth: Fix help messageBen Widawsky2019-07-181-1/+1
| * | intel_synth: Small code cleanup to remove if ladderBen Widawsky2019-07-181-28/+10
| * | intel_synth: Make family explicit and matchBen Widawsky2019-07-181-2/+6
| * | intel_synth: Minor code cleanupsBen Widawsky2019-07-181-2/+6
* | | synth_intel: rename for consistency with #1184Dan Ravensloft2019-07-181-4/+4
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* | Merge pull request #1184 from whitequark/synth-better-labelsClifford Wolf2019-07-185-17/+21
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| * | synth_ecp5: rename dram to lutram everywhere.whitequark2019-07-164-13/+13
| * | synth_{ice40,ecp5}: more sensible pass label naming.whitequark2019-07-162-5/+9
* | | Merge pull request #1204 from smunaut/fix_1187David Shah2019-07-172-4/+4
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