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* Call shregmap twice -- once for variable, another for fixedEddie Hung2019-04-052-8/+14
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* Move dffinit til after abcEddie Hung2019-04-053-2/+2
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* Merge branch 'eddie/fix_retime' into xc7srlEddie Hung2019-04-054-11/+12
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| * Move techamp t:$_DFF_?N? to before abc callEddie Hung2019-04-051-2/+2
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| * RetryEddie Hung2019-04-051-1/+1
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| * Resolve @daveshah1 comment, update synth_xilinx helpEddie Hung2019-04-052-7/+9
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| * synth_xilinx to techmap FFs after abc call, otherwise -retime failsEddie Hung2019-04-051-3/+3
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* | techmap inside map_cells stageEddie Hung2019-04-052-2/+1
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* | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-0/+1
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| * | Missing techmap entry in helpEddie Hung2019-04-041-0/+1
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* | | Use soft-logic, not LUT3 instantiationEddie Hung2019-04-041-4/+2
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* | | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-12/+12
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| * | synth_xilinx to map_cells before map_lutsEddie Hung2019-04-041-12/+12
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* | Cleanup commentsEddie Hung2019-04-041-5/+4
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* | t:$dff* -> t:$dff t:$dffeEddie Hung2019-04-041-2/+2
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* | -nosrl meant when -nobramEddie Hung2019-04-031-1/+1
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* | Remove duplicate STARTUPE2Eddie Hung2019-04-031-1/+0
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* | Disable shregmap in synth_xilinx if -retimeEddie Hung2019-04-031-3/+3
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* | synth_xilinx to use shregmap with -minlen 3Eddie Hung2019-03-251-2/+2
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* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-222-24/+31
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| * xilinx: Add keep attribute where appropriateDavid Shah2019-03-222-25/+31
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Add '-nosrl' option to synth_xilinxEddie Hung2019-03-211-6/+16
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* | Fine tune cells_map.vEddie Hung2019-03-201-19/+15
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* | Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable lengthEddie Hung2019-03-191-53/+20
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* | Add support for variable length Xilinx SRL > 128Eddie Hung2019-03-191-11/+67
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* | Restore original synth_xilinx commandsEddie Hung2019-03-191-1/+2
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* | Fix spacingEddie Hung2019-03-191-1/+1
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* | Fix INIT for variable length SRs that have been bumped up oneEddie Hung2019-03-191-1/+1
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* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-191-2/+4
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| * Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873Clifford Wolf2019-03-191-2/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Only accept <128 for variable length, only if $shiftx exclusiveEddie Hung2019-03-161-5/+1
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* | Cleanup synth_xilinxEddie Hung2019-03-152-3/+2
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* | WorkingEddie Hung2019-03-152-47/+78
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* | Reverse bits in INIT parameter for Xilinx, since MSB is shifted firstEddie Hung2019-03-141-16/+32
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* | MisspellEddie Hung2019-03-141-1/+1
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* | Revert "Add shregmap -init_msb_first and use in synth_xilinx"Eddie Hung2019-03-141-3/+2
| | | | | | | | This reverts commit 26ecbc1aee1dca1c186ab2b51835d74f67bc3e75.
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-1433-402/+1656
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| * Remove ice40/cells_sim.v hack to avoid warning for blocking memory writesClifford Wolf2019-03-121-19/+0
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix typo in ice40_braminit help msgClifford Wolf2019-03-091-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #859 from smunaut/ice40_braminitClifford Wolf2019-03-094-37/+212
| |\ | | | | | | iCE40 BRAM primitives init from file
| | * ice40: Run ice40_braminit pass by defaultSylvain Munaut2019-03-081-0/+1
| | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| | * ice40: Add ice40_braminit pass to allow initialization of BRAM from fileSylvain Munaut2019-03-083-37/+211
| | | | | | | | | | | | | | | | | | | | | | | | This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will initialize content from a hex file. Same behavior is imlemented in the simulation model and in a new pass for actual synthesis Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | Add link to SF2 / igloo2 macro library guideClifford Wolf2019-03-071-21/+24
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improvements in sf2 cells_sim.vClifford Wolf2019-03-062-30/+251
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add sf2 techmap rules for more FF typesClifford Wolf2019-03-061-25/+39
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Refactor SF2 iobuf insertion, Add clkint insertionClifford Wolf2019-03-063-83/+152
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improvements in SF2 flow and demoClifford Wolf2019-03-052-8/+23
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #842 from litghost/merge_upstreamClifford Wolf2019-03-0510-176/+570
| |\ \ | | | | | | | | Changes required for VPR place and route in synth_xilinx
| | * | Revert BRAM WRITE_MODE changes.Keith Rothman2019-03-041-12/+12
| | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | * | Revert FF models to include IS_x_INVERTED parameters.Keith Rothman2019-03-011-6/+34
| | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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