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* techlibs/intel: Clean up MakefileBen Widawsky2019-08-051-15/+5
| | | | | | | Use GNU make's foreach iterator and remove nonexistent files. Gmake is already a requirement of the build system. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
* Merge pull request #1239 from mmicko/mingw_fixClifford Wolf2019-08-023-6/+6
|\ | | | | Fix formatting for msys2 mingw build
| * Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-013-6/+6
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* | RST -> RSTBRST for RAMB8BWEREddie Hung2019-07-291-3/+3
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* Merge branch 'ZirconiumX-synth_intel_m9k'Clifford Wolf2019-07-254-5/+11
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| * intel: Map M9K BRAM only on families that have itDan Ravensloft2019-07-234-5/+12
| | | | | | | | | | | | | | | | This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM.
* | Merge pull request #1218 from ZirconiumX/synth_intel_iopadsClifford Wolf2019-07-251-8/+8
|\ \ | | | | | | intel: Make -noiopads the default
| * | intel: Make -noiopads the defaultDan Ravensloft2019-07-241-8/+8
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* | | Merge pull request #1224 from YosysHQ/xilinx_fix_ffEddie Hung2019-07-251-2/+2
|\ \ \ | |/ / |/| | xilinx: Fix missing cell name underscore in cells_map.v
| * | xilinx: Fix missing cell name underscore in cells_map.vDavid Shah2019-07-251-2/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | ice40: Fix test_dsp_model.shDavid Shah2019-07-191-1/+1
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | ice40/cells_sim.v: Fix sign of J and K partial productsDavid Shah2019-07-191-5/+7
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | ice40/cells_sim.v: LSB of A/B only signed in 8x8 modeDavid Shah2019-07-191-2/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Add tests for all combinations of A and B signedness for comb mulEddie Hung2019-07-192-1/+229
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* | | Don't copy ref if exists alreadyEddie Hung2019-07-191-1/+3
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* | Merge pull request #1208 from ZirconiumX/intel_cleanupsDavid Shah2019-07-181-29/+14
|\ \ | | | | | | Assorted synth_intel cleanups from @bwidawsk
| * | synth_intel: Use stringfDan Ravensloft2019-07-181-7/+2
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| * | synth_intel: s/not family/no family/Dan Ravensloft2019-07-181-2/+2
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| * | intel_synth: Fix help messageBen Widawsky2019-07-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cyclonev has been a "supported" family since the initial commit. The old commit message suggested to use a10gx which is incorrect. Aside from the obvious lack of functional change due to this just being a help message, users who were previously using "a10gx" for "cyclonev" will also have no functional change by using "cyclonev" instead. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * | intel_synth: Small code cleanup to remove if ladderBen Widawsky2019-07-181-28/+10
| | | | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * | intel_synth: Make family explicit and matchBen Widawsky2019-07-181-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | The help and code default to MAX10 for the family, however the couple of if ladders defaulted to cycloneive. Fix this inconsistency and the next patch will clean it up. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * | intel_synth: Minor code cleanupsBen Widawsky2019-07-181-2/+6
| | | | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
* | | synth_intel: rename for consistency with #1184Dan Ravensloft2019-07-181-4/+4
|/ / | | | | | | Also fix a typo in the help message.
* | Merge pull request #1184 from whitequark/synth-better-labelsClifford Wolf2019-07-185-17/+21
|\ \ | | | | | | synth_{ice40,ecp5}: more sensible pass label naming
| * | synth_ecp5: rename dram to lutram everywhere.whitequark2019-07-164-13/+13
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| * | synth_{ice40,ecp5}: more sensible pass label naming.whitequark2019-07-162-5/+9
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* | | Merge pull request #1204 from smunaut/fix_1187David Shah2019-07-172-4/+4
|\ \ \ | | | | | | | | ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map
| * | | ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port mapSylvain Munaut2019-07-162-4/+4
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new mapping introduced in 437fec0d88b4a2ad172edf0d1a861a38845f3b1d needed matching adaptation when converting and optimizing LUTs during the relut process Fixes #1187 (Diagnosis of the issue by @daveshah1 on IRC) Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* / | gen_lut to return correctly sized LUT maskEddie Hung2019-07-161-1/+1
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* | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fixEddie Hung2019-07-168-29/+120
|\ \ | |/ |/| abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
| * $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequarkEddie Hung2019-07-157-8/+8
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| * ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUTEddie Hung2019-07-131-9/+7
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| * Use Const::from_string() not its constructor...Eddie Hung2019-07-121-1/+1
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| * Off by oneEddie Hung2019-07-121-1/+1
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| * Fix spacingEddie Hung2019-07-121-1/+1
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| * Remove double pushEddie Hung2019-07-121-1/+0
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| * Map to and from this box if -abc9Eddie Hung2019-07-121-2/+3
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| * ice40_opt to handle this box and opt back to SB_LUT4Eddie Hung2019-07-121-0/+48
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| * Add new box to cells_sim.vEddie Hung2019-07-121-2/+25
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| * _ABC macro will map and unmap to this new boxEddie Hung2019-07-122-0/+34
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| * Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 boxEddie Hung2019-07-123-25/+13
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* | Merge pull request #1183 from whitequark/ice40-always-relutClifford Wolf2019-07-121-11/+5
|\ \ | |/ |/| synth_ice40: switch -relut to be always on
| * synth_ice40: switch -relut to be always on.whitequark2019-07-111-10/+4
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| * synth_ice40: fix help text typo. NFC.whitequark2019-07-111-1/+1
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* | Merge pull request #1182 from koriakin/xc6s-bramEddie Hung2019-07-119-8/+598
|\ \ | | | | | | synth_xilinx: Initial Spartan 6 block RAM inference support.
| * | synth_xilinx: Initial Spartan 6 block RAM inference support.Marcin Kościelnicki2019-07-119-8/+598
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* / xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ↵Marcin Kościelnicki2019-07-112-6/+6
|/ | | | ISE/Vivado.
* Merge pull request #1180 from YosysHQ/eddie/no_abc9_retimeEddie Hung2019-07-103-6/+15
|\ | | | | Error out if -abc9 and -retime specified
| * Error out if -abc9 and -retime specifiedEddie Hung2019-07-103-6/+15
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* | Merge pull request #1148 from YosysHQ/xc7muxEddie Hung2019-07-106-49/+414
|\ \ | |/ |/| synth_xilinx to infer wide multiplexers using new '-widemux <min>' option
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