| Commit message (Expand) | Author | Age | Files | Lines |
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| | * | | | | | Run "opt_expr -fine" instead of "wreduce" due to #1213 | Eddie Hung | 2019-08-07 | 1 | -2/+1 |
| | * | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-07 | 6 | -123/+277 |
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| | | * | | | | Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes | David Shah | 2019-08-07 | 1 | -101/+244 |
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| | | | * | | | | ecp5: Make cells_sim.v consistent with nextpnr | David Shah | 2019-08-07 | 1 | -101/+244 |
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| | | * | | | | Merge pull request #1249 from mmicko/anlogic_fix | Clifford Wolf | 2019-08-07 | 1 | -16/+8 |
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| | | | * | | | anlogic : Fix alu mapping | Miodrag Milanovic | 2019-08-03 | 1 | -16/+8 |
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| | | * / / | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs | Clifford Wolf | 2019-08-06 | 1 | -0/+19 |
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| | | * | | Merge pull request #1239 from mmicko/mingw_fix | Clifford Wolf | 2019-08-02 | 3 | -6/+6 |
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| | | | * | | Fix formatting for msys2 mingw build using GetSize | Miodrag Milanovic | 2019-08-01 | 3 | -6/+6 |
| * | | | | | DSP48E1 sim model: add SIMD tests | David Shah | 2019-08-08 | 3 | -3/+113 |
| * | | | | | DSP48E1 model: test CE inputs | David Shah | 2019-08-08 | 2 | -7/+17 |
| * | | | | | DSP48E1 sim model: fix seq tests and add preadder tests | David Shah | 2019-08-08 | 2 | -6/+91 |
| * | | | | | DSP48E1 sim model: seq test working | David Shah | 2019-08-08 | 3 | -16/+60 |
| * | | | | | DSP48E1 sim model: Comb, no pre-adder, mode working | David Shah | 2019-08-08 | 2 | -8/+13 |
| * | | | | | [wip] sim model testing | David Shah | 2019-08-08 | 4 | -15/+77 |
| * | | | | | [wip] sim model testing | David Shah | 2019-08-08 | 3 | -40/+360 |
| * | | | | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-07 | 1 | -6/+82 |
| * | | | | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-06 | 1 | -23/+120 |
| * | | | | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-06 | 1 | -8/+75 |
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| * | | | | Trim Y_WIDTH | Eddie Hung | 2019-08-01 | 1 | -5/+3 |
| * | | | | Add DSP_SIGNEDONLY back | Eddie Hung | 2019-08-01 | 1 | -0/+16 |
| * | | | | DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH | Eddie Hung | 2019-08-01 | 2 | -5/+12 |
| * | | | | Change $__softmul back to $mul | Eddie Hung | 2019-08-01 | 1 | -0/+1 |
| * | | | | Revert "Do not do sign extension in techmap; let packer do it" | Eddie Hung | 2019-08-01 | 1 | -5/+14 |
| * | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-01 | 6 | -18/+24 |
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| | * | | | RST -> RSTBRST for RAMB8BWER | Eddie Hung | 2019-07-29 | 1 | -3/+3 |
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| | * | | Merge branch 'ZirconiumX-synth_intel_m9k' | Clifford Wolf | 2019-07-25 | 4 | -5/+11 |
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| | | * | | intel: Map M9K BRAM only on families that have it | Dan Ravensloft | 2019-07-23 | 4 | -5/+12 |
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| | * | | Merge pull request #1218 from ZirconiumX/synth_intel_iopads | Clifford Wolf | 2019-07-25 | 1 | -8/+8 |
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| | | * | | intel: Make -noiopads the default | Dan Ravensloft | 2019-07-24 | 1 | -8/+8 |
| | * | | | Merge pull request #1224 from YosysHQ/xilinx_fix_ff | Eddie Hung | 2019-07-25 | 1 | -2/+2 |
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| | | * | | xilinx: Fix missing cell name underscore in cells_map.v | David Shah | 2019-07-25 | 1 | -2/+2 |
| * | | | | Fix B_WIDTH > DSP_B_MAXWIDTH case | Eddie Hung | 2019-08-01 | 1 | -32/+14 |
| * | | | | Do not compute sign bit if result is zero | Eddie Hung | 2019-07-31 | 1 | -1/+2 |
| * | | | | For signed multipliers, compute sign bit separately... | Eddie Hung | 2019-07-31 | 1 | -23/+42 |
| * | | | | Fix spacing | Eddie Hung | 2019-07-26 | 1 | -3/+3 |
| * | | | | Add copyright header, comment on cascade | Eddie Hung | 2019-07-24 | 1 | -4/+34 |
| * | | | | Typo for Y_WIDTH | Eddie Hung | 2019-07-23 | 1 | -1/+1 |
| * | | | | Remove debug | Eddie Hung | 2019-07-22 | 1 | -1/+0 |
| * | | | | Rename according to vendor doc TN1295 | Eddie Hung | 2019-07-22 | 1 | -0/+1 |
| * | | | | opt and wreduce necessary for -dsp | Eddie Hung | 2019-07-22 | 1 | -2/+4 |
| * | | | | Use minimum sized width wires | Eddie Hung | 2019-07-22 | 1 | -7/+13 |
| * | | | | Indirection via $__soft_mul | Eddie Hung | 2019-07-19 | 2 | -9/+10 |
| * | | | | Do not do sign extension in techmap; let packer do it | Eddie Hung | 2019-07-19 | 1 | -14/+5 |
| * | | | | Do not $mul -> $__mul if A and B are less than maxwidth | Eddie Hung | 2019-07-19 | 1 | -1/+3 |
| * | | | | Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold | Eddie Hung | 2019-07-19 | 1 | -1/+1 |
| * | | | | Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too | Eddie Hung | 2019-07-19 | 1 | -28/+68 |
| * | | | | Merge branch 'xc7dsp' into ice40dsp | Eddie Hung | 2019-07-19 | 1 | -1/+1 |
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| | * | | | | Fix typo in B | Eddie Hung | 2019-07-19 | 1 | -1/+1 |
| | * | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-07-18 | 15 | -84/+164 |
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