| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Merge pull request #911 from mmicko/gowin-nobram | Clifford Wolf | 2019-04-22 | 1 | -1/+1 |
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| | * | Make nobram false by default for gowin | Miodrag Milanovic | 2019-04-02 | 1 | -1/+1 |
| * | | Revert "synth_* with -retime option now calls abc with -D 1 as well" | Eddie Hung | 2019-04-18 | 11 | -15/+15 |
| * | | Merge branch 'master' into eddie/fix_retime | Eddie Hung | 2019-04-18 | 4 | -44/+69 |
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| | * \ | Merge pull request #928 from litghost/add_xc7_sim_models | Eddie Hung | 2019-04-12 | 3 | -41/+60 |
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| | | * | | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. | Keith Rothman | 2019-04-12 | 3 | -52/+14 |
| | | * | | Fix LUT6_2 definition. | Keith Rothman | 2019-04-09 | 1 | -3/+3 |
| | | * | | Add additional cells sim models for core 7-series primatives. | Keith Rothman | 2019-04-09 | 1 | -0/+57 |
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| | * / | Fixing issues in CycloneV cell sim | Diego | 2019-04-11 | 1 | -3/+9 |
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| * | | synth_* with -retime option now calls abc with -D 1 as well | Eddie Hung | 2019-04-10 | 11 | -15/+15 |
| * | | Move techamp t:$_DFF_?N? to before abc call | Eddie Hung | 2019-04-05 | 1 | -2/+2 |
| * | | Retry | Eddie Hung | 2019-04-05 | 1 | -1/+1 |
| * | | Resolve @daveshah1 comment, update synth_xilinx help | Eddie Hung | 2019-04-05 | 2 | -7/+9 |
| * | | synth_xilinx to techmap FFs after abc call, otherwise -retime fails | Eddie Hung | 2019-04-05 | 1 | -3/+3 |
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| * | xilinx: Add keep attribute where appropriate | David Shah | 2019-03-22 | 2 | -25/+31 |
| * | Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 | Clifford Wolf | 2019-03-19 | 1 | -2/+4 |
| * | Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes | Clifford Wolf | 2019-03-12 | 1 | -19/+0 |
| * | Fix typo in ice40_braminit help msg | Clifford Wolf | 2019-03-09 | 1 | -1/+1 |
| * | Merge pull request #859 from smunaut/ice40_braminit | Clifford Wolf | 2019-03-09 | 4 | -37/+212 |
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| | * | ice40: Run ice40_braminit pass by default | Sylvain Munaut | 2019-03-08 | 1 | -0/+1 |
| | * | ice40: Add ice40_braminit pass to allow initialization of BRAM from file | Sylvain Munaut | 2019-03-08 | 3 | -37/+211 |
| * | | Add link to SF2 / igloo2 macro library guide | Clifford Wolf | 2019-03-07 | 1 | -21/+24 |
| * | | Improvements in sf2 cells_sim.v | Clifford Wolf | 2019-03-06 | 2 | -30/+251 |
| * | | Add sf2 techmap rules for more FF types | Clifford Wolf | 2019-03-06 | 1 | -25/+39 |
| * | | Refactor SF2 iobuf insertion, Add clkint insertion | Clifford Wolf | 2019-03-06 | 3 | -83/+152 |
| * | | Improvements in SF2 flow and demo | Clifford Wolf | 2019-03-05 | 2 | -8/+23 |
| * | | Merge pull request #842 from litghost/merge_upstream | Clifford Wolf | 2019-03-05 | 10 | -176/+570 |
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| | * | | Revert BRAM WRITE_MODE changes. | Keith Rothman | 2019-03-04 | 1 | -12/+12 |
| | * | | Revert FF models to include IS_x_INVERTED parameters. | Keith Rothman | 2019-03-01 | 1 | -6/+34 |
| | * | | Use singular for disabling of DRAM or BRAM inference. | Keith Rothman | 2019-03-01 | 1 | -13/+13 |
| | * | | Modify arguments to match existing style. | Keith Rothman | 2019-03-01 | 1 | -6/+6 |
| | * | | Changes required for VPR place and route synth_xilinx. | Keith Rothman | 2019-03-01 | 11 | -221/+587 |
| * | | | Merge pull request #850 from daveshah1/ecp5_warn_conflict | Clifford Wolf | 2019-03-05 | 1 | -2/+7 |
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| | * | | | ecp5: Demote conflicting FF init values to a warning | David Shah | 2019-03-04 | 1 | -2/+7 |
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| * / / | Use "write_edif -pvector bra" for Xilinx EDIF files | Clifford Wolf | 2019-03-05 | 1 | -1/+1 |
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| * | | Fix ECP5 cells_sim for iverilog | Miodrag Milanovic | 2019-03-01 | 1 | -2/+3 |
| * | | Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode | Clifford Wolf | 2019-02-28 | 1 | -2/+2 |
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| | * | | ice40: use 2 bits for READ/WRITE MODE for SB_RAM map | Elms | 2019-02-28 | 1 | -2/+2 |
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| * | | Reduce amount of trailing whitespace in code base | Larry Doolittle | 2019-02-28 | 6 | -19/+19 |
| * | | Merge pull request #794 from daveshah1/ecp5improve | Clifford Wolf | 2019-02-28 | 7 | -12/+388 |
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| | * | ecp5: Compatibility with Migen AsyncResetSynchronizer | David Shah | 2019-02-25 | 2 | -0/+20 |
| | * | ecp5: Add DDRDLLA | David Shah | 2019-02-19 | 1 | -0/+9 |
| | * | ecp5: Add DELAYF/DELAYG blackboxes | David Shah | 2019-02-19 | 1 | -0/+18 |
| | * | ecp5: Add ECLKSYNCB blackbox | David Shah | 2019-02-13 | 1 | -1/+7 |
| | * | ecp5: Full set of IO-related blackboxes | David Shah | 2019-02-12 | 1 | -0/+102 |
| | * | ecp5: Support for flipflop initialisation | David Shah | 2019-01-22 | 3 | -4/+199 |
| | * | ecp5: Add LSRMODE to flipflops for PRLD support | David Shah | 2019-01-21 | 1 | -7/+16 |
| | * | ecp5: More blackboxes | David Shah | 2019-01-21 | 1 | -0/+17 |
| | * | ecp5: Increase threshold for ALU mapping | David Shah | 2019-01-21 | 1 | -1/+1 |
| * | | techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module | Larry Doolittle | 2019-02-26 | 1 | -22/+22 |
