abc9_ops: add -prep_bypass for auto bypass boxes; refactor

Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier

6 files changed, 127 insertions, 761 deletions

diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 9984290a6..d4d863831 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -54,8 +54,6 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc5v_dsp_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_dsp_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_dsp_map.v))
 
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_map.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_unmap.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_model.v))
 
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
deleted file mode 100644
index 1d733a650..000000000
--- a/techlibs/xilinx/abc9_map.v
+++ /dev/null
@@ -1,432 +0,0 @@
-/*
- *  yosys -- Yosys Open SYnthesis Suite
- *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *                2019  Eddie Hung    <eddie@fpgeh.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-// The following techmapping rules are intended to be run (with -max_iter 1)
-//   before invoking the `abc9` pass in order to transform the design into
-//   a format that it understands.
-
-// Attach a (combinatorial) black-box onto the output
-//   of thes LUTRAM primitives to capture their
-//   asynchronous read behaviour
-module RAM32X1D (
-  output DPO, SPO,
-  (* techmap_autopurge *) input  D,
-  (* techmap_autopurge *) input  WCLK,
-  (* techmap_autopurge *) input  WE,
-  (* techmap_autopurge *) input  A0, A1, A2, A3, A4,
-  (* techmap_autopurge *) input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
-);
-  parameter INIT = 32'h0;
-  parameter IS_WCLK_INVERTED = 1'b0;
-  wire $DPO, $SPO;
-  RAM32X1D #(
-    .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .DPO($DPO), .SPO($SPO),
-    .D(D), .WCLK(WCLK), .WE(WE),
-    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
-    .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
-  );
-  $__ABC9_RAM6 spo (.A($SPO), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO));
-  $__ABC9_RAM6 dpo (.A($DPO), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
-endmodule
-
-module RAM64X1D (
-  output DPO, SPO,
-  (* techmap_autopurge *) input  D,
-  (* techmap_autopurge *) input  WCLK,
-  (* techmap_autopurge *) input  WE,
-  (* techmap_autopurge *) input  A0, A1, A2, A3, A4, A5,
-  (* techmap_autopurge *) input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
-);
-  parameter INIT = 64'h0;
-  parameter IS_WCLK_INVERTED = 1'b0;
-  wire $DPO, $SPO;
-  RAM64X1D #(
-    .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .DPO($DPO), .SPO($SPO),
-    .D(D), .WCLK(WCLK), .WE(WE),
-    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
-    .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
-  );
-  $__ABC9_RAM6 spo (.A($SPO), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO));
-  $__ABC9_RAM6 dpo (.A($DPO), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
-endmodule
-
-module RAM128X1D (
-  output       DPO, SPO,
-  (* techmap_autopurge *) input        D,
-  (* techmap_autopurge *) input        WCLK,
-  (* techmap_autopurge *) input        WE,
-  (* techmap_autopurge *) input  [6:0] A, DPRA
-);
-  parameter INIT = 128'h0;
-  parameter IS_WCLK_INVERTED = 1'b0;
-  wire $DPO, $SPO;
-  RAM128X1D #(
-    .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .DPO($DPO), .SPO($SPO),
-    .D(D), .WCLK(WCLK), .WE(WE),
-    .A(A),
-    .DPRA(DPRA)
-  );
-  $__ABC9_RAM7 spo (.A($SPO), .S(A), .Y(SPO));
-  $__ABC9_RAM7 dpo (.A($DPO), .S(DPRA), .Y(DPO));
-endmodule
-
-module RAM32M (
-  output [1:0] DOA,
-  output [1:0] DOB,
-  output [1:0] DOC,
-  output [1:0] DOD,
-  (* techmap_autopurge *) input [4:0] ADDRA,
-  (* techmap_autopurge *) input [4:0] ADDRB,
-  (* techmap_autopurge *) input [4:0] ADDRC,
-  (* techmap_autopurge *) input [4:0] ADDRD,
-  (* techmap_autopurge *) input [1:0] DIA,
-  (* techmap_autopurge *) input [1:0] DIB,
-  (* techmap_autopurge *) input [1:0] DIC,
-  (* techmap_autopurge *) input [1:0] DID,
-  (* techmap_autopurge *) input WCLK,
-  (* techmap_autopurge *) input WE
-);
-  parameter [63:0] INIT_A = 64'h0000000000000000;
-  parameter [63:0] INIT_B = 64'h0000000000000000;
-  parameter [63:0] INIT_C = 64'h0000000000000000;
-  parameter [63:0] INIT_D = 64'h0000000000000000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  wire [1:0] $DOA, $DOB, $DOC, $DOD;
-  RAM32M #(
-    .INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D),
-    .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .DOA($DOA), .DOB($DOB), .DOC($DOC), .DOD($DOD),
-    .WCLK(WCLK), .WE(WE),
-    .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
-    .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
-  );
-  $__ABC9_RAM6 doa0 (.A($DOA[0]), .S({1'b1, ADDRA}), .Y(DOA[0]));
-  $__ABC9_RAM6 doa1 (.A($DOA[1]), .S({1'b1, ADDRA}), .Y(DOA[1]));
-  $__ABC9_RAM6 dob0 (.A($DOB[0]), .S({1'b1, ADDRB}), .Y(DOB[0]));
-  $__ABC9_RAM6 dob1 (.A($DOB[1]), .S({1'b1, ADDRB}), .Y(DOB[1]));
-  $__ABC9_RAM6 doc0 (.A($DOC[0]), .S({1'b1, ADDRC}), .Y(DOC[0]));
-  $__ABC9_RAM6 doc1 (.A($DOC[1]), .S({1'b1, ADDRC}), .Y(DOC[1]));
-  $__ABC9_RAM6 dod0 (.A($DOD[0]), .S({1'b1, ADDRD}), .Y(DOD[0]));
-  $__ABC9_RAM6 dod1 (.A($DOD[1]), .S({1'b1, ADDRD}), .Y(DOD[1]));
-endmodule
-
-module RAM64M (
-  output DOA,
-  output DOB,
-  output DOC,
-  output DOD,
-  (* techmap_autopurge *) input [5:0] ADDRA,
-  (* techmap_autopurge *) input [5:0] ADDRB,
-  (* techmap_autopurge *) input [5:0] ADDRC,
-  (* techmap_autopurge *) input [5:0] ADDRD,
-  (* techmap_autopurge *) input DIA,
-  (* techmap_autopurge *) input DIB,
-  (* techmap_autopurge *) input DIC,
-  (* techmap_autopurge *) input DID,
-  (* techmap_autopurge *) input WCLK,
-  (* techmap_autopurge *) input WE
-);
-  parameter [63:0] INIT_A = 64'h0000000000000000;
-  parameter [63:0] INIT_B = 64'h0000000000000000;
-  parameter [63:0] INIT_C = 64'h0000000000000000;
-  parameter [63:0] INIT_D = 64'h0000000000000000;
-  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  wire $DOA, $DOB, $DOC, $DOD;
-  RAM64M #(
-    .INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D),
-    .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .DOA($DOA), .DOB($DOB), .DOC($DOC), .DOD($DOD),
-    .WCLK(WCLK), .WE(WE),
-    .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
-    .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
-  );
-  $__ABC9_RAM6 doa (.A($DOA), .S(ADDRA), .Y(DOA));
-  $__ABC9_RAM6 dob (.A($DOB), .S(ADDRB), .Y(DOB));
-  $__ABC9_RAM6 doc (.A($DOC), .S(ADDRC), .Y(DOC));
-  $__ABC9_RAM6 dod (.A($DOD), .S(ADDRD), .Y(DOD));
-endmodule
-
-module SRL16 (
-  output Q,
-  (* techmap_autopurge *) input A0, A1, A2, A3, CLK, D
-);
-  parameter [15:0] INIT = 16'h0000;
-  wire $Q;
-  SRL16 #(
-    .INIT(INIT),
-  ) _TECHMAP_REPLACE_ (
-    .Q($Q),
-    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CLK(CLK), .D(D)
-  );
-  $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
-endmodule
-
-module SRL16E (
-  output Q,
-  (* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D
-);
-  parameter [15:0] INIT = 16'h0000;
-  parameter [0:0] IS_CLK_INVERTED = 1'b0;
-  wire $Q;
-  SRL16E #(
-    .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .Q($Q),
-    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
-  );
-  $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
-endmodule
-
-module SRLC16 (
-  output Q, Q15,
-  (* techmap_autopurge *) input A0, A1, A2, A3, CLK, D
-);
-  parameter [15:0] INIT = 16'h0000;
-  wire $Q;
-  SRLC16 #(
-    .INIT(INIT),
-  ) _TECHMAP_REPLACE_ (
-    .Q($Q), .Q(Q15),
-    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CLK(CLK), .D(D)
-  );
-  $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
-endmodule
-
-module SRLC16E (
-  output Q, Q15,
-  (* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D
-);
-  parameter [15:0] INIT = 16'h0000;
-  parameter [0:0] IS_CLK_INVERTED = 1'b0;
-  wire $Q;
-  SRLC16E #(
-    .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .Q($Q), .Q(Q15),
-    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
-  );
-  $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
-endmodule
-
-module SRLC32E (
-  output Q,
-  output Q31,
-  (* techmap_autopurge *) input [4:0] A,
-  (* techmap_autopurge *) input CE, CLK, D
-);
-  parameter [31:0] INIT = 32'h00000000;
-  parameter [0:0] IS_CLK_INVERTED = 1'b0;
-  wire $Q;
-  SRLC32E #(
-    .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .Q($Q), .Q31(Q31),
-    .A(A), .CE(CE), .CLK(CLK), .D(D)
-  );
-  $__ABC9_RAM6 q (.A($Q), .S({1'b1, A}), .Y(Q));
-endmodule
-
-module DSP48E1 (
-    (* techmap_autopurge *) output [29:0] ACOUT,
-    (* techmap_autopurge *) output [17:0] BCOUT,
-    (* techmap_autopurge *) output reg CARRYCASCOUT,
-    (* techmap_autopurge *) output reg [3:0] CARRYOUT,
-    (* techmap_autopurge *) output reg MULTSIGNOUT,
-    (* techmap_autopurge *) output OVERFLOW,
-    (* techmap_autopurge *) output reg signed [47:0] P,
-    (* techmap_autopurge *) output PATTERNBDETECT,
-    (* techmap_autopurge *) output PATTERNDETECT,
-    (* techmap_autopurge *) output [47:0] PCOUT,
-    (* techmap_autopurge *) output UNDERFLOW,
-    (* techmap_autopurge *) input signed [29:0] A,
-    (* techmap_autopurge *) input [29:0] ACIN,
-    (* techmap_autopurge *) input [3:0] ALUMODE,
-    (* techmap_autopurge *) input signed [17:0] B,
-    (* techmap_autopurge *) input [17:0] BCIN,
-    (* techmap_autopurge *) input [47:0] C,
-    (* techmap_autopurge *) input CARRYCASCIN,
-    (* techmap_autopurge *) input CARRYIN,
-    (* techmap_autopurge *) input [2:0] CARRYINSEL,
-    (* techmap_autopurge *) input CEA1,
-    (* techmap_autopurge *) input CEA2,
-    (* techmap_autopurge *) input CEAD,
-    (* techmap_autopurge *) input CEALUMODE,
-    (* techmap_autopurge *) input CEB1,
-    (* techmap_autopurge *) input CEB2,
-    (* techmap_autopurge *) input CEC,
-    (* techmap_autopurge *) input CECARRYIN,
-    (* techmap_autopurge *) input CECTRL,
-    (* techmap_autopurge *) input CED,
-    (* techmap_autopurge *) input CEINMODE,
-    (* techmap_autopurge *) input CEM,
-    (* techmap_autopurge *) input CEP,
-    (* techmap_autopurge *) input CLK,
-    (* techmap_autopurge *) input [24:0] D,
-    (* techmap_autopurge *) input [4:0] INMODE,
-    (* techmap_autopurge *) input MULTSIGNIN,
-    (* techmap_autopurge *) input [6:0] OPMODE,
-    (* techmap_autopurge *) input [47:0] PCIN,
-    (* techmap_autopurge *) input RSTA,
-    (* techmap_autopurge *) input RSTALLCARRYIN,
-    (* techmap_autopurge *) input RSTALUMODE,
-    (* techmap_autopurge *) input RSTB,
-    (* techmap_autopurge *) input RSTC,
-    (* techmap_autopurge *) input RSTCTRL,
-    (* techmap_autopurge *) input RSTD,
-    (* techmap_autopurge *) input RSTINMODE,
-    (* techmap_autopurge *) input RSTM,
-    (* techmap_autopurge *) input RSTP
-);
-    parameter integer ACASCREG = 1;
-    parameter integer ADREG = 1;
-    parameter integer ALUMODEREG = 1;
-    parameter integer AREG = 1;
-    parameter AUTORESET_PATDET = "NO_RESET";
-    parameter A_INPUT = "DIRECT";
-    parameter integer BCASCREG = 1;
-    parameter integer BREG = 1;
-    parameter B_INPUT = "DIRECT";
-    parameter integer CARRYINREG = 1;
-    parameter integer CARRYINSELREG = 1;
-    parameter integer CREG = 1;
-    parameter integer DREG = 1;
-    parameter integer INMODEREG = 1;
-    parameter integer MREG = 1;
-    parameter integer OPMODEREG = 1;
-    parameter integer PREG = 1;
-    parameter SEL_MASK = "MASK";
-    parameter SEL_PATTERN = "PATTERN";
-    parameter USE_DPORT = "FALSE";
-    parameter USE_MULT = "MULTIPLY";
-    parameter USE_PATTERN_DETECT = "NO_PATDET";
-    parameter USE_SIMD = "ONE48";
-    parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
-    parameter [47:0] PATTERN = 48'h000000000000;
-    parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
-    parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
-    parameter [0:0] IS_CLK_INVERTED = 1'b0;
-    parameter [4:0] IS_INMODE_INVERTED = 5'b0;
-    parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
-
-    wire [47:0] $P, $PCOUT;
-
-    DSP48E1 #(
-        .ACASCREG(ACASCREG),
-        .ADREG(ADREG),
-        .ALUMODEREG(ALUMODEREG),
-        .AREG(AREG),
-        .AUTORESET_PATDET(AUTORESET_PATDET),
-        .A_INPUT(A_INPUT),
-        .BCASCREG(BCASCREG),
-        .BREG(BREG),
-        .B_INPUT(B_INPUT),
-        .CARRYINREG(CARRYINREG),
-        .CARRYINSELREG(CARRYINSELREG),
-        .CREG(CREG),
-        .DREG(DREG),
-        .INMODEREG(INMODEREG),
-        .MREG(MREG),
-        .OPMODEREG(OPMODEREG),
-        .PREG(PREG),
-        .SEL_MASK(SEL_MASK),
-        .SEL_PATTERN(SEL_PATTERN),
-        .USE_DPORT(USE_DPORT),
-        .USE_MULT(USE_MULT),
-        .USE_PATTERN_DETECT(USE_PATTERN_DETECT),
-        .USE_SIMD(USE_SIMD),
-        .MASK(MASK),
-        .PATTERN(PATTERN),
-        .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
-        .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
-        .IS_CLK_INVERTED(IS_CLK_INVERTED),
-        .IS_INMODE_INVERTED(IS_INMODE_INVERTED),
-        .IS_OPMODE_INVERTED(IS_OPMODE_INVERTED)
-    ) _TECHMAP_REPLACE_ (
-        .ACOUT(ACOUT),
-        .BCOUT(BCOUT),
-        .CARRYCASCOUT(CARRYCASCOUT),
-        .CARRYOUT(CARRYOUT),
-        .MULTSIGNOUT(MULTSIGNOUT),
-        .OVERFLOW(OVERFLOW),
-        .P($P),
-        .PATTERNBDETECT(PATTERNBDETECT),
-        .PATTERNDETECT(PATTERNDETECT),
-        .PCOUT($PCOUT),
-        .UNDERFLOW(UNDERFLOW),
-        .A(A),
-        .ACIN(ACIN),
-        .ALUMODE(ALUMODE),
-        .B(B),
-        .BCIN(BCIN),
-        .C(C),
-        .CARRYCASCIN(CARRYCASCIN),
-        .CARRYIN(CARRYIN),
-        .CARRYINSEL(CARRYINSEL),
-        .CEA1(CEA1),
-        .CEA2(CEA2),
-        .CEAD(CEAD),
-        .CEALUMODE(CEALUMODE),
-        .CEB1(CEB1),
-        .CEB2(CEB2),
-        .CEC(CEC),
-        .CECARRYIN(CECARRYIN),
-        .CECTRL(CECTRL),
-        .CED(CED),
-        .CEINMODE(CEINMODE),
-        .CEM(CEM),
-        .CEP(CEP),
-        .CLK(CLK),
-        .D(D),
-        .INMODE(INMODE),
-        .MULTSIGNIN(MULTSIGNIN),
-        .OPMODE(OPMODE),
-        .PCIN(PCIN),
-        .RSTA(RSTA),
-        .RSTALLCARRYIN(RSTALLCARRYIN),
-        .RSTALUMODE(RSTALUMODE),
-        .RSTB(RSTB),
-        .RSTC(RSTC),
-        .RSTCTRL(RSTCTRL),
-        .RSTD(RSTD),
-        .RSTINMODE(RSTINMODE),
-        .RSTM(RSTM),
-        .RSTP(RSTP)
-    );
-    $__ABC9_DSP48E1 #(
-        .ADREG(ADREG),
-        .AREG(AREG),
-        .BREG(BREG),
-        .CREG(CREG),
-        .DREG(DREG),
-        .MREG(MREG),
-        .PREG(PREG),
-        .USE_DPORT(USE_DPORT),
-        .USE_MULT(USE_MULT)
-    ) dsp_comb (
-        .$A(A), .$B(B), .$C(C), .$D(D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
-endmodule
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v
index 2d109ef8a..db44ff00b 100644
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -37,174 +37,3 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
     (S1 => O) = 273;
   endspecify
 endmodule
-
-// Box to emulate async behaviour of FDC*
-(* abc9_box, lib_whitebox *)
-module \$__ABC9_ASYNC0 (input A, S, output Y);
-  assign Y = S ? 1'b0 : A;
-  specify
-    (A => Y) = 0;
-    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
-    (S => Y) = 764;
-  endspecify
-endmodule
-
-// Box to emulate async behaviour of FDP*
-(* abc9_box, lib_whitebox *)
-module \$__ABC9_ASYNC1 (input A, S, output Y);
-  assign Y = S ? 1'b1 : A;
-  specify
-    (A => Y) = 0;
-    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
-    (S => Y) = 764;
-  endspecify
-endmodule
-
-// Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32}
-//   Necessary since RAMD* and SRL* have both combinatorial (i.e.
-//   same-cycle read operation) and sequential (write operation
-//   is only committed on the next clock edge).
-//   To model the combinatorial path, such cells have to be split
-//   into comb and seq parts, with this box modelling only the former.
-(* abc9_box *)
-module \$__ABC9_RAM6 (input A, input [5:0] S, output Y);
-  specify
-    (A    => Y) =   0;
-    (S[0] => Y) = 642;
-    (S[1] => Y) = 631;
-    (S[2] => Y) = 472;
-    (S[3] => Y) = 407;
-    (S[4] => Y) = 238;
-    (S[5] => Y) = 127;
-  endspecify
-endmodule
-// Box to emulate comb/seq behaviour of RAM128
-(* abc9_box *)
-module \$__ABC9_RAM7 (input A, input [6:0] S, output Y);
-  specify
-    (A    => Y) = 0;
-                                                    // https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L867
-    (S[0] => Y) = 642 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
-    (S[1] => Y) = 631 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
-    (S[2] => Y) = 472 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
-    (S[3] => Y) = 407 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
-    (S[4] => Y) = 238 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
-    (S[5] => Y) = 127 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
-    (S[6] => Y) = 0 + 296 /* to select F7BMUX */ + 174 /* CMUX */;
-  endspecify
-endmodule
-
-// Boxes used to represent the comb behaviour of DSP48E1
-(* abc9_box *)
-module $__ABC9_DSP48E1 (
-    input [29:0] $A,
-    input [17:0] $B,
-    input [47:0] $C,
-    input [24:0] $D,
-    input [47:0] $P,
-    input [47:0] $PCIN,
-    input [47:0] $PCOUT,
-    output [47:0] P,
-    output [47:0] PCOUT
-);
-    parameter integer ADREG = 1;
-    parameter integer AREG = 1;
-    parameter integer BREG = 1;
-    parameter integer CREG = 1;
-    parameter integer DREG = 1;
-    parameter integer MREG = 1;
-    parameter integer PREG = 1;
-    parameter USE_DPORT = "FALSE";
-    parameter USE_MULT = "MULTIPLY";
-
-    function integer \A.P.comb ;
-    begin
-        if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE")     \A.P.comb = 2823;
-        else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.P.comb = 3806;
-        else if (USE_MULT == "NONE" && USE_DPORT == "FALSE")    \A.P.comb = 1523;
-    end
-    endfunction
-    function integer \A.PCOUT.comb ;
-    begin
-        if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE")     \A.PCOUT.comb = 2970;
-        else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.PCOUT.comb = 3954;
-        else if (USE_MULT == "NONE" && USE_DPORT == "FALSE")    \A.PCOUT.comb = 1671;
-    end
-    endfunction
-    function integer \B.P.comb ;
-    begin
-        if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE")     \B.P.comb = 2690;
-        else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.P.comb = 2690;
-        else if (USE_MULT == "NONE" && USE_DPORT == "FALSE")    \B.P.comb = 1509;
-    end
-    endfunction
-    function integer \B.PCOUT.comb ;
-    begin
-        if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE")     \B.PCOUT.comb = 2838;
-        else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.PCOUT.comb = 2838;
-        else if (USE_MULT == "NONE" && USE_DPORT == "FALSE")    \B.PCOUT.comb = 1658;
-    end
-    endfunction
-    function integer \C.P.comb ;
-    begin
-        if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE")     \C.P.comb = 1325;
-        else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.P.comb = 1325;
-        else if (USE_MULT == "NONE" && USE_DPORT == "FALSE")    \C.P.comb = 1325;
-    end
-    endfunction
-    function integer \C.PCOUT.comb ;
-    begin
-        if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE")     \C.PCOUT.comb = 1474;
-        else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.PCOUT.comb = 1474;
-        else if (USE_MULT == "NONE" && USE_DPORT == "FALSE")    \C.PCOUT.comb = 1474;
-    end
-    endfunction
-    function integer \D.P.comb ;
-    begin
-        if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE")      \D.P.comb = 3717;
-    end
-    endfunction
-    function integer \D.PCOUT.comb ;
-    begin
-        if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE")      \D.PCOUT.comb = 3700;
-    end
-    endfunction
-
-	specify
-		($P *> P) 			= 0;
-		($PCOUT *> PCOUT)	= 0;
-	endspecify
-
-    // Identical comb delays to DSP48E1 in cells_sim.v
-    generate
-        if (PREG == 0 && MREG == 0 && AREG == 0 && ADREG == 0)
-            specify
-                ($A *> P) =      \A.P.comb ();
-                ($A *> PCOUT) =  \A.PCOUT.comb ();
-            endspecify
-
-        if (PREG == 0 && MREG == 0 && BREG == 0)
-            specify
-                ($B *> P) =      \B.P.comb ();
-                ($B *> PCOUT) =  \B.PCOUT.comb ();
-            endspecify
-
-        if (PREG == 0 && CREG == 0)
-            specify
-                ($C *> P) =      \C.P.comb ();
-                ($C *> PCOUT) =  \C.PCOUT.comb ();
-            endspecify
-
-        if (PREG == 0 && MREG == 0 && ADREG == 0 && DREG == 0)
-            specify
-                ($D *> P) =      \D.P.comb ();
-                ($D *> PCOUT) =  \D.PCOUT.comb ();
-            endspecify
-
-        if (PREG == 0)
-            specify
-                ($PCIN *> P) =       1107;
-                ($PCIN *> PCOUT) =   1255;
-            endspecify
-    endgenerate
-endmodule
diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v
deleted file mode 100644
index 49a7bd88c..000000000
--- a/techlibs/xilinx/abc9_unmap.v
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- *  yosys -- Yosys Open SYnthesis Suite
- *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *                2019  Eddie Hung    <eddie@fpgeh.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-// ============================================================================
-
-(* techmap_celltype = "$__ABC9_ASYNC0 $__ABC9_ASYNC1" *)
-module $__ABC9_ASYNC01(input A, S, output Y);
-  assign Y = A;
-endmodule
-
-module $__ABC9_RAM6(input A, input [5:0] S, output Y);
-  assign Y = A;
-endmodule
-module $__ABC9_RAM7(input A, input [6:0] S, output Y);
-  assign Y = A;
-endmodule
-
-module $__ABC9_DSP48E1(
-    input [29:0] $A,
-    input [17:0] $B,
-    input [47:0] $C,
-    input [24:0] $D,
-    input [47:0] $P,
-    input [47:0] $PCIN,
-    input [47:0] $PCOUT,
-    output [47:0] P,
-    output [47:0] PCOUT
-);
-    parameter integer ADREG = 1;
-    parameter integer AREG = 1;
-    parameter integer BREG = 1;
-    parameter integer CREG = 1;
-    parameter integer DREG = 1;
-    parameter integer MREG = 1;
-    parameter integer PREG = 1;
-    parameter USE_DPORT = "FALSE";
-    parameter USE_MULT = "MULTIPLY";
-
-    assign P = $P, PCOUT = $PCOUT;
-endmodule
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 25df3a865..a6eb9a90e 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -524,10 +524,10 @@ module FDRE (
     $setup(R , posedge C &&& !IS_C_INVERTED, 404);
     $setup(R , negedge C &&&  IS_C_INVERTED, 404);
     // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
-    if (!IS_C_INVERTED && R ^ IS_R_INVERTED)        (posedge C => (Q : 1'b0)) = 303;
-    if ( IS_C_INVERTED && R ^ IS_R_INVERTED)        (negedge C => (Q : 1'b0)) = 303;
-    if (!IS_C_INVERTED && R ~^ IS_R_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
-    if ( IS_C_INVERTED && R ~^ IS_R_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+    if (!IS_C_INVERTED && R != IS_R_INVERTED)        (posedge C => (Q : 1'b0)) = 303;
+    if ( IS_C_INVERTED && R != IS_R_INVERTED)        (negedge C => (Q : 1'b0)) = 303;
+    if (!IS_C_INVERTED && R == IS_R_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+    if ( IS_C_INVERTED && R == IS_R_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
   endspecify
 endmodule
 
@@ -589,10 +589,10 @@ module FDSE (
     $setup(S , posedge C &&& !IS_C_INVERTED, 404);
     $setup(S , negedge C &&&  IS_C_INVERTED, 404);
     // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
-    if (!IS_C_INVERTED && S ^ IS_S_INVERTED)        (posedge C => (Q : 1'b1)) = 303;
-    if ( IS_C_INVERTED && S ^ IS_S_INVERTED)        (negedge C => (Q : 1'b1)) = 303;
-    if (!IS_C_INVERTED && S ~^ IS_S_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
-    if ( IS_C_INVERTED && S ~^ IS_S_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+    if (!IS_C_INVERTED && S != IS_S_INVERTED)       (posedge C => (Q : 1'b1)) = 303;
+    if ( IS_C_INVERTED && S != IS_S_INVERTED)       (negedge C => (Q : 1'b1)) = 303;
+    if (!IS_C_INVERTED && S == IS_S_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+    if ( IS_C_INVERTED && S == IS_S_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
   endspecify
 endmodule
 
@@ -656,6 +656,7 @@ module FDRSE (
       Q <= d;
 endmodule
 
+(* abc9_box, lib_whitebox *)
 module FDCE (
   output reg Q,
   (* clkbuf_sink *)
@@ -691,13 +692,15 @@ module FDCE (
     $setup(CLR, posedge C &&& !IS_C_INVERTED, 404);
     $setup(CLR, negedge C &&&  IS_C_INVERTED, 404);
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
-    //if (!IS_CLR_INVERTED) (posedge CLR => (Q : 1'b0)) = 764; // Captured by $__ABC9_ASYNC0
-    //if ( IS_CLR_INVERTED) (negedge CLR => (Q : 1'b0)) = 764; // Captured by $__ABC9_ASYNC0
-    if (!IS_C_INVERTED && CLR ~^ IS_CLR_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
-    if ( IS_C_INVERTED && CLR ~^ IS_CLR_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+    if (IS_CLR_INVERTED != CLR) (CLR => Q) = 764; // Technically, this should be an edge sensitive path
+                                                  // but for facilitating a bypass box, let's pretend it's
+                                                  // a simple path
+    if (!IS_C_INVERTED && CLR == IS_CLR_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+    if ( IS_C_INVERTED && CLR == IS_CLR_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
   endspecify
 endmodule
 
+(* abc9_box, lib_whitebox *)
 module FDCE_1 (
   output reg Q,
   (* clkbuf_sink *)
@@ -717,11 +720,14 @@ module FDCE_1 (
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
     $setup(CLR, negedge C, 404);
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
-    //(posedge CLR => (Q : 1'b0)) = 764; // Captured by $__ABC9_ASYNC0
+    if (CLR) (CLR => Q) = 764; // Technically, this should be an edge sensitive path
+                               // but for facilitating a bypass box, let's pretend it's
+                               // a simple path
     if (!CLR && CE) (negedge C => (Q : D)) = 303;
   endspecify
 endmodule
 
+//(* abc9_box, lib_whitebox *)
 module FDPE (
   output reg Q,
   (* clkbuf_sink *)
@@ -756,13 +762,15 @@ module FDPE (
     $setup(PRE, posedge C &&& !IS_C_INVERTED, 404);
     $setup(PRE, negedge C &&&  IS_C_INVERTED, 404);
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
-    //if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1
-    //if ( IS_PRE_INVERTED) (negedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1
-    if (!IS_C_INVERTED && PRE ~^ IS_PRE_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
-    if ( IS_C_INVERTED && PRE ~^ IS_PRE_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+    if (IS_PRE_INVERTED != PRE) (PRE => Q) = 764; // Technically, this should be an edge sensitive path
+                                                  // but for facilitating a bypass box, let's pretend it's
+                                                  // a simple path
+    if (!IS_C_INVERTED && PRE == IS_PRE_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+    if ( IS_C_INVERTED && PRE == IS_PRE_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
   endspecify
 endmodule
 
+(* abc9_box, lib_whitebox *)
 module FDPE_1 (
   output reg Q,
   (* clkbuf_sink *)
@@ -782,8 +790,9 @@ module FDPE_1 (
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
     $setup(PRE, negedge C, 404);
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
-    //if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1
-    //if (IS_PRE_INVERTED)  (negedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1
+    if (PRE) (PRE => Q) = 764; // Technically, this should be an edge sensitive path
+                               // but for facilitating a bypass box, let's pretend it's
+                               // a simple path
     if (!PRE && CE) (negedge C => (Q : D)) = 303;
   endspecify
 endmodule
@@ -1395,6 +1404,7 @@ module RAM16X1D_1 (
   always @(negedge clk) if (WE) mem[a] <= D;
 endmodule
 
+(* abc9_box, lib_whitebox *)
 module RAM32X1D (
   output DPO, SPO,
   input  D,
@@ -1441,15 +1451,15 @@ module RAM32X1D (
     if (!IS_WCLK_INVERTED) (posedge WCLK => (DPO : 1'bx)) = 1153;
     if ( IS_WCLK_INVERTED) (posedge WCLK => (SPO : D))    = 1153;
     if ( IS_WCLK_INVERTED) (negedge WCLK => (DPO : 1'bx)) = 1153;
-    // Captured by $__ABC9_RAM6
-    //({A0,DPRA0} => {SPO,DPO}) = 642;
-    //({A1,DPRA1} => {SPO,DPO}) = 631;
-    //({A2,DPRA2} => {SPO,DPO}) = 472;
-    //({A3,DPRA3} => {SPO,DPO}) = 407;
-    //({A4,DPRA4} => {SPO,DPO}) = 238;
+    (A0 => SPO) = 642; (DPRA0 => DPO) = 642;
+    (A1 => SPO) = 632; (DPRA1 => DPO) = 631;
+    (A2 => SPO) = 472; (DPRA2 => DPO) = 472;
+    (A3 => SPO) = 407; (DPRA3 => DPO) = 407;
+    (A4 => SPO) = 238; (DPRA4 => DPO) = 238;
   endspecify
 endmodule
 
+(* abc9_box, lib_whitebox *)
 module RAM32X1D_1 (
   output DPO, SPO,
   input  D,
@@ -1491,15 +1501,15 @@ module RAM32X1D_1 (
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
     if (WE) (negedge WCLK => (SPO : D))    = 1153;
     if (WE) (negedge WCLK => (DPO : 1'bx)) = 1153;
-    // Captured by $__ABC9_RAM6
-    //({A0,DPRA0} => {SPO,DPO}) = 642;
-    //({A1,DPRA1} => {SPO,DPO}) = 631;
-    //({A2,DPRA2} => {SPO,DPO}) = 472;
-    //({A3,DPRA3} => {SPO,DPO}) = 407;
-    //({A4,DPRA4} => {SPO,DPO}) = 238;
+    (A0 => SPO) = 642; (DPRA0 => DPO) = 642;
+    (A1 => SPO) = 632; (DPRA1 => DPO) = 631;
+    (A2 => SPO) = 472; (DPRA2 => DPO) = 472;
+    (A3 => SPO) = 407; (DPRA3 => DPO) = 407;
+    (A4 => SPO) = 238; (DPRA4 => DPO) = 238;
   endspecify
 endmodule
 
+(* abc9_box, lib_whitebox *)
 module RAM64X1D (
   output DPO, SPO,
   input  D,
@@ -1549,13 +1559,12 @@ module RAM64X1D (
     if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DPO : 1'bx)) = 1153;
     if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (SPO : D))    = 1153;
     if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153;
-    // Captured by $__ABC9_RAM6
-    //({A0,DPRA0} => {SPO,DPO}) = 642;
-    //({A1,DPRA1} => {SPO,DPO}) = 631;
-    //({A2,DPRA2} => {SPO,DPO}) = 472;
-    //({A3,DPRA3} => {SPO,DPO}) = 407;
-    //({A4,DPRA4} => {SPO,DPO}) = 238;
-    //({A5,DPRA5} => {SPO,DPO}) = 127;
+    (A0 => SPO) = 642; (DPRA0 => DPO) = 642;
+    (A1 => SPO) = 632; (DPRA1 => DPO) = 631;
+    (A2 => SPO) = 472; (DPRA2 => DPO) = 472;
+    (A3 => SPO) = 407; (DPRA3 => DPO) = 407;
+    (A4 => SPO) = 238; (DPRA4 => DPO) = 238;
+    (A5 => SPO) = 127; (DPRA5 => DPO) = 127;
   endspecify
 endmodule
 
@@ -1598,9 +1607,16 @@ module RAM64X1D_1 (
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
     if (WE) (negedge WCLK => (SPO : D))    = 1153;
     if (WE) (negedge WCLK => (DPO : 1'bx)) = 1153;
+    (A0 => SPO) = 642; (DPRA0 => DPO) = 642;
+    (A1 => SPO) = 632; (DPRA1 => DPO) = 631;
+    (A2 => SPO) = 472; (DPRA2 => DPO) = 472;
+    (A3 => SPO) = 407; (DPRA3 => DPO) = 407;
+    (A4 => SPO) = 238; (DPRA4 => DPO) = 238;
+    (A5 => SPO) = 127; (DPRA5 => DPO) = 127;
   endspecify
 endmodule
 
+(* abc9_box, lib_whitebox *)
 module RAM128X1D (
   output       DPO, SPO,
   input        D,
@@ -1645,21 +1661,20 @@ module RAM128X1D (
     if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (SPO : D))    = 1153 + 217 /* to cross F7AMUX */ + 175 /* AMUX */;
     if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
 `endif
-    // Captured by $__ABC9_RAM7
-    //(A[0] => SPO) = 642 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
-    //(A[1] => SPO) = 631 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
-    //(A[2] => SPO) = 472 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
-    //(A[3] => SPO) = 407 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
-    //(A[4] => SPO) = 238 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
-    //(A[5] => SPO) = 127 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
-    //(A[6] => SPO) = 0 + 276 /* to select F7AMUX */ + 175 /* AMUX */;
-    //(DPRA[0] => DPO) = 642 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
-    //(DPRA[1] => DPO) = 631 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
-    //(DPRA[2] => DPO) = 472 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
-    //(DPRA[3] => DPO) = 407 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
-    //(DPRA[4] => DPO) = 238 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
-    //(DPRA[5] => DPO) = 127 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
-    //(DPRA[6] => DPO) = 0 + 296 /* to select MUXF7 */ + 174 /* CMUX */;
+    (A[0] => SPO) = 642 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+    (A[1] => SPO) = 631 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+    (A[2] => SPO) = 472 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+    (A[3] => SPO) = 407 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+    (A[4] => SPO) = 238 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+    (A[5] => SPO) = 127 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+    (A[6] => SPO) = 0 + 276 /* to select F7AMUX */ + 175 /* AMUX */;
+    (DPRA[0] => DPO) = 642 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    (DPRA[1] => DPO) = 631 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    (DPRA[2] => DPO) = 472 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    (DPRA[3] => DPO) = 407 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    (DPRA[4] => DPO) = 238 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    (DPRA[5] => DPO) = 127 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    (DPRA[6] => DPO) = 0 + 296 /* to select MUXF7 */ + 174 /* CMUX */;
   endspecify
 endmodule
 
@@ -1683,6 +1698,7 @@ endmodule
 
 // Multi port.
 
+(* abc9_box, lib_whitebox *)
 module RAM32M (
   output [1:0] DOA,
   output [1:0] DOB,
@@ -1779,12 +1795,11 @@ module RAM32M (
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
     if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD[1] : DID[1])) = 1190;
     if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD[1] : DID[1])) = 1190;
-    // Captured by $__ABC9_RAM6
-    //({{2{ADDRA[0]}},{2{ADDRB[0]}},{2{ADDRC[0]}},{2{ADDRD[0]}}} => {DOA,DOB,DOC,DOD}) = 642;
-    //({{2{ADDRA[1]}},{2{ADDRB[1]}},{2{ADDRC[1]}},{2{ADDRD[1]}}} => {DOA,DOB,DOC,DOD}) = 631;
-    //({{2{ADDRA[2]}},{2{ADDRB[2]}},{2{ADDRC[2]}},{2{ADDRD[2]}}} => {DOA,DOB,DOC,DOD}) = 472;
-    //({{2{ADDRA[3]}},{2{ADDRB[3]}},{2{ADDRC[3]}},{2{ADDRD[3]}}} => {DOA,DOB,DOC,DOD}) = 407;
-    //({{2{ADDRA[4]}},{2{ADDRB[4]}},{2{ADDRC[4]}},{2{ADDRD[4]}}} => {DOA,DOB,DOC,DOD}) = 238;
+    (ADDRA[0] *> DOA) = 642; (ADDRB[0] *> DOB) = 642; (ADDRC[0] *> DOC) = 642; (ADDRD[0] *> DOD) = 642;
+    (ADDRA[1] *> DOA) = 631; (ADDRB[1] *> DOB) = 631; (ADDRC[1] *> DOC) = 631; (ADDRD[1] *> DOD) = 631;
+    (ADDRA[2] *> DOA) = 472; (ADDRB[2] *> DOB) = 472; (ADDRC[2] *> DOC) = 472; (ADDRD[2] *> DOD) = 472;
+    (ADDRA[3] *> DOA) = 407; (ADDRB[3] *> DOB) = 407; (ADDRC[3] *> DOC) = 407; (ADDRD[3] *> DOD) = 407;
+    (ADDRA[4] *> DOA) = 238; (ADDRB[4] *> DOB) = 238; (ADDRC[4] *> DOC) = 238; (ADDRD[4] *> DOD) = 238;
   endspecify
 endmodule
 
@@ -1857,6 +1872,7 @@ module RAM32M16 (
     end
 endmodule
 
+(* abc9_box, lib_whitebox *)
 module RAM64M (
   output       DOA,
   output       DOB,
@@ -1935,12 +1951,11 @@ module RAM64M (
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
     if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD : DID)) = 1163;
     if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD : DID)) = 1163;
-    // Captured by $__ABC9_RAM6
-    //({ADDRA[0],ADDRB[0],ADDRC[0],ADDRD[0]} => {DOA,DOB,DOC,DOD}) = 642;
-    //({ADDRA[1],ADDRB[1],ADDRC[1],ADDRD[1]} => {DOA,DOB,DOC,DOD}) = 631;
-    //({ADDRA[2],ADDRB[2],ADDRC[2],ADDRD[2]} => {DOA,DOB,DOC,DOD}) = 472;
-    //({ADDRA[3],ADDRB[3],ADDRC[3],ADDRD[3]} => {DOA,DOB,DOC,DOD}) = 407;
-    //({ADDRA[4],ADDRB[4],ADDRC[4],ADDRD[4]} => {DOA,DOB,DOC,DOD}) = 238;
+    (ADDRA[0] => DOA) = 642; (ADDRB[0] => DOB) = 642; (ADDRC[0] => DOC) = 642; (ADDRD[0] => DOD) = 642;
+    (ADDRA[1] => DOA) = 631; (ADDRB[1] => DOB) = 631; (ADDRC[1] => DOC) = 631; (ADDRD[1] => DOD) = 631;
+    (ADDRA[2] => DOA) = 472; (ADDRB[2] => DOB) = 472; (ADDRC[2] => DOC) = 472; (ADDRD[2] => DOD) = 472;
+    (ADDRA[3] => DOA) = 407; (ADDRB[3] => DOB) = 407; (ADDRC[3] => DOC) = 407; (ADDRD[3] => DOD) = 407;
+    (ADDRA[4] => DOA) = 238; (ADDRB[4] => DOB) = 238; (ADDRC[4] => DOC) = 238; (ADDRD[4] => DOD) = 238;
   endspecify
 endmodule
 
@@ -2057,6 +2072,7 @@ endmodule
 
 // Shift registers.
 
+(* abc9_box, lib_whitebox *)
 module SRL16 (
   output Q,
   input A0, A1, A2, A3,
@@ -2075,14 +2091,14 @@ module SRL16 (
     (posedge CLK => (Q : 1'bx)) = 1472;
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
     $setup(D , posedge CLK, 173);
-    // Captured by $__ABC9_RAM6
-    //(A0 => Q) = 631;
-    //(A1 => Q) = 472;
-    //(A2 => Q) = 407;
-    //(A3 => Q) = 238;
+    (A0 => Q) = 631;
+    (A1 => Q) = 472;
+    (A2 => Q) = 407;
+    (A3 => Q) = 238;
   endspecify
 endmodule
 
+(* abc9_box, lib_whitebox *)
 module SRL16E (
   output Q,
   input A0, A1, A2, A3, CE,
@@ -2108,16 +2124,19 @@ module SRL16E (
     $setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173);
     $setup(D , negedge CLK &&&  IS_CLK_INVERTED, 173);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
+    if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : D)) = 1472;
+    if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : D)) = 1472;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
     if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1472;
     if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1472;
-    // Captured by $__ABC9_RAM6
-    //(A0 => Q) = 631;
-    //(A1 => Q) = 472;
-    //(A2 => Q) = 407;
-    //(A3 => Q) = 238;
+    (A0 => Q) = 631;
+    (A1 => Q) = 472;
+    (A2 => Q) = 407;
+    (A3 => Q) = 238;
   endspecify
 endmodule
 
+(* abc9_box, lib_whitebox *)
 module SRLC16 (
   output Q,
   output Q15,
@@ -2134,18 +2153,20 @@ module SRLC16 (
   always @(posedge CLK) r <= { r[14:0], D };
 
   specify
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
-    (posedge CLK => (Q : 1'bx)) = 1472;
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
     $setup(D , posedge CLK, 173);
-    // Captured by $__ABC9_RAM6
-    //(A0 => Q) = 631;
-    //(A1 => Q) = 472;
-    //(A2 => Q) = 407;
-    //(A3 => Q) = 238;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
+    (posedge CLK => (Q : 1'bx)) = 1472;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904
+    (posedge CLK => (Q15 : 1'bx)) = 1114;
+    (A0 => Q) = 631;
+    (A1 => Q) = 472;
+    (A2 => Q) = 407;
+    (A3 => Q) = 238;
   endspecify
 endmodule
 
+(* abc9_box, lib_whitebox *)
 module SRLC16E (
   output Q,
   output Q15,
@@ -2172,18 +2193,23 @@ module SRLC16E (
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
     $setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173);
     $setup(D , negedge CLK &&&  IS_CLK_INVERTED, 173);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
+    $setup(CE, posedge CLK &&& !IS_CLK_INVERTED, 109);
+    $setup(CE, negedge CLK &&&  IS_CLK_INVERTED, 109);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
     if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : D)) = 1472;
     if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : D)) = 1472;
-    // Captured by $__ABC9_RAM6
-    //(A0 => Q) = 642;
-    //(A1 => Q) = 631;
-    //(A2 => Q) = 472;
-    //(A3 => Q) = 407;
-    //(A4 => Q) = 238;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904
+    if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q15 : 1'bx)) = 1114;
+    if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q15 : 1'bx)) = 1114;
+    (A0 => Q) = 631;
+    (A1 => Q) = 472;
+    (A2 => Q) = 407;
+    (A3 => Q) = 238;
   endspecify
 endmodule
 
+(* abc9_box, lib_whitebox *)
 module SRLC32E (
   output Q,
   output Q31,
@@ -2211,18 +2237,20 @@ module SRLC32E (
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
     $setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173);
     $setup(D , negedge CLK &&&  IS_CLK_INVERTED, 173);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
+    $setup(CE, posedge CLK &&& !IS_CLK_INVERTED, 109);
+    $setup(CE, negedge CLK &&&  IS_CLK_INVERTED, 109);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
     if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1472;
     if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1472;
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904
-    if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1114;
-    if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1114;
-    // Captured by $__ABC9_RAM6
-    //(A0 => Q) = 642;
-    //(A1 => Q) = 631;
-    //(A2 => Q) = 472;
-    //(A3 => Q) = 407;
-    //(A4 => Q) = 238;
+    if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q31 : 1'bx)) = 1114;
+    if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q31 : 1'bx)) = 1114;
+    (A[0] => Q) = 642;
+    (A[1] => Q) = 631;
+    (A[2] => Q) = 472;
+    (A[3] => Q) = 407;
+    (A[4] => Q) = 238;
   endspecify
 endmodule
 
@@ -2990,6 +3018,8 @@ endmodule
 
 // Virtex 6, Series 7.
 
+(* abc9_box=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG),
+   lib_whitebox=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG) *)
 module DSP48E1 (
     output [29:0] ACOUT,
     output [17:0] BCOUT,
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index d6ca9e57e..d05715ec2 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -598,7 +598,7 @@ struct SynthXilinxPass : public ScriptPass
 		if (check_label("map_ffs", "('-abc9' only)")) {
 			if (abc9 || help_mode) {
 				if (dff || help_mode)
-					run("zinit -all", "('-dff' only)");
+					run("zinit -all t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "('-dff' only)");
 				run("techmap -map " + ff_map_file);
 			}
 		}
@@ -615,7 +615,6 @@ struct SynthXilinxPass : public ScriptPass
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
 							"will use timing for 'xc7' instead.\n", family.c_str());
-				run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
 				run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v");
 				std::string abc9_opts;
 				std::string k = "synth_xilinx.abc9.W";
@@ -630,7 +629,6 @@ struct SynthXilinxPass : public ScriptPass
 				if (dff)
 					abc9_opts += " -dff";
 				run("abc9" + abc9_opts);
-				run("techmap -map +/xilinx/abc9_unmap.v");
 			}
 			else {
 				std::string abc_opts;