aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/xilinx
Commit message (Expand)AuthorAgeFilesLines
* synth_xilinx to use _ABC macro, and perform muxpack againEddie Hung2019-06-211-5/+5
* Add $__XILINX_MUXF78 to preserve entire boxEddie Hung2019-06-213-7/+28
* Fix alignmentEddie Hung2019-06-211-1/+1
* Add FIXME about need for -mux4Eddie Hung2019-06-211-0/+2
* Since muxcover uses MUX4s, blast them back to gates hereEddie Hung2019-06-211-0/+7
* Expand synth -coarse without wreduce, move muxcoverEddie Hung2019-06-211-12/+24
* Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abcEddie Hung2019-06-201-0/+1
* mux_map to drop sign bit, and eliminate 'bx-esEddie Hung2019-06-201-13/+47
* Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-181-29/+27
|\
| * Really permute Xilinx LUT mappings as default LUT6.I5:A6Eddie Hung2019-06-181-16/+16
| * Revert "Fix (do not) permute LUT inputs, but permute mux selects"Eddie Hung2019-06-181-33/+31
* | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-181-31/+33
|\|
| * Fix (do not) permute LUT inputs, but permute mux selectsEddie Hung2019-06-181-31/+33
* | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-171-9/+8
|\|
| * Fix copy-pasta issueEddie Hung2019-06-171-9/+8
* | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-172-33/+59
|\|
| * Permute INIT for +/xilinx/lut_map.vEddie Hung2019-06-171-32/+58
| * Simplify commentEddie Hung2019-06-171-1/+1
* | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-171-5/+5
|\|
| * Update LUT7/8 delays to take account for [ABC]OUTMUX delayEddie Hung2019-06-171-5/+5
| * Try -W 300Eddie Hung2019-06-171-1/+2
* | Try -W 300Eddie Hung2019-06-161-1/+2
* | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-151-2/+2
|\|
| * Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> OEddie Hung2019-06-151-2/+2
* | Revert "Remove wide mux inference"Eddie Hung2019-06-144-3/+194
|/
* As per @daveshah1 remove async DFF timing from xilinxEddie Hung2019-06-141-2/+2
* Add XC7_WIRE_DELAY macro to synth_xilinx.ccEddie Hung2019-06-141-1/+3
* Update delays based on SymbiFlow/prjxray-dbEddie Hung2019-06-141-12/+13
* Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}Eddie Hung2019-06-144-3/+3
* Remove WIP ABC9 flop supportEddie Hung2019-06-142-18/+18
* Make doc consistentEddie Hung2019-06-141-1/+1
* Fix name clashEddie Hung2019-06-131-4/+8
* Move neg-pol to pos-pol mapping from ff_map to cells_map.vEddie Hung2019-06-121-0/+8
* Reduce diff with masterEddie Hung2019-06-121-1/+1
* Fix spacingEddie Hung2019-06-121-6/+6
* Remove wide mux inferenceEddie Hung2019-06-124-194/+3
* Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"Eddie Hung2019-06-121-1/+1
* Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"Eddie Hung2019-06-121-1/+1
* Add "-W' wire delay arg to abc9, use from synth_xilinxEddie Hung2019-06-111-1/+1
* Disable dist RAM boxes due to comb loopEddie Hung2019-06-111-2/+2
* Remove #ifndef ABCEddie Hung2019-06-111-4/+0
* Revert "Revert "Move ff_map back after ABC for shregmap""Eddie Hung2019-06-101-5/+5
* Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"Eddie Hung2019-06-101-2/+2
* Comment out muxpack (currently broken)Eddie Hung2019-06-071-2/+2
* $__XILINX_MUX_ -> $__XILINX_SHIFTXEddie Hung2019-06-062-11/+11
* Fix muxcover and its techmappingEddie Hung2019-06-062-3/+3
* Run muxpack and muxcover in synth_xilinxEddie Hung2019-06-062-1/+18
* Remove abc_flop attributes for nowEddie Hung2019-06-061-56/+10
* Update abc attributes on FD*E_1Eddie Hung2019-06-051-6/+26
* CleanupEddie Hung2019-06-052-17/+0