iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Re-added clean after techmap in synth_xilinx	Clifford Wolf	2019-04-22	1	-0/+2
*	Merge branch 'master' into map_cells_before_map_luts	Eddie Hung	2019-04-21	5	-56/+76
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\| *	Revert "synth_* with -retime option now calls abc with -D 1 as well"	Eddie Hung	2019-04-18	1	-2/+2
\| *	Merge branch 'master' into eddie/fix_retime	Eddie Hung	2019-04-18	3	-41/+60
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\| \| *	Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.	Keith Rothman	2019-04-12	3	-52/+14
\| \| *	Fix LUT6_2 definition.	Keith Rothman	2019-04-09	1	-3/+3
\| \| *	Add additional cells sim models for core 7-series primatives.	Keith Rothman	2019-04-09	1	-0/+57
\| * \|	synth_* with -retime option now calls abc with -D 1 as well	Eddie Hung	2019-04-10	1	-2/+2
\| * \|	Move techamp t:$_DFF_?N? to before abc call	Eddie Hung	2019-04-05	1	-2/+2
\| * \|	Retry	Eddie Hung	2019-04-05	1	-1/+1
\| * \|	Resolve @daveshah1 comment, update synth_xilinx help	Eddie Hung	2019-04-05	2	-7/+9
\| * \|	synth_xilinx to techmap FFs after abc call, otherwise -retime fails	Eddie Hung	2019-04-05	1	-3/+3
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* \|	Missing techmap entry in help	Eddie Hung	2019-04-04	1	-0/+1
* \|	synth_xilinx to map_cells before map_luts	Eddie Hung	2019-04-04	1	-12/+12
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*	xilinx: Add keep attribute where appropriate	David Shah	2019-03-22	2	-25/+31
*	Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873	Clifford Wolf	2019-03-19	1	-2/+4
*	Merge pull request #842 from litghost/merge_upstream	Clifford Wolf	2019-03-05	10	-176/+570
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\| *	Revert BRAM WRITE_MODE changes.	Keith Rothman	2019-03-04	1	-12/+12
\| *	Revert FF models to include IS_x_INVERTED parameters.	Keith Rothman	2019-03-01	1	-6/+34
\| *	Use singular for disabling of DRAM or BRAM inference.	Keith Rothman	2019-03-01	1	-13/+13
\| *	Modify arguments to match existing style.	Keith Rothman	2019-03-01	1	-6/+6
\| *	Changes required for VPR place and route synth_xilinx.	Keith Rothman	2019-03-01	11	-221/+587
* \|	Use "write_edif -pvector bra" for Xilinx EDIF files	Clifford Wolf	2019-03-05	1	-1/+1
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*	Fix typographical and grammatical errors and inconsistencies.	whitequark	2019-01-02	1	-1/+1
*	Add support for Xilinx PS7 block	Eddie Hung	2018-11-10	2	-0/+624
*	xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.	Tim 'mithro' Ansell	2018-10-08	1	-3/+2
*	Add inout ports to cells_xtra.v	Clifford Wolf	2018-10-04	2	-2/+14
*	xilinx: Adding missing inout IO port to IOBUF	Tim Ansell	2018-10-03	1	-0/+1
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Improving vpr output support.	Tim 'mithro' Ansell	2018-04-18	2	-3/+36
*	Squelch trailing whitespace, including meta-whitespace	Larry Doolittle	2018-03-11	1	-8/+8
*	Add Xilinx RAM64X1D and RAM128X1D simulation models	Clifford Wolf	2018-03-07	4	-23/+30
*	Add techlibs/xilinx/lut2lut.v	Clifford Wolf	2017-07-10	2	-0/+66
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Added black box modules for all the 7-series design elements (as listed in ug...	Clifford Wolf	2016-03-19	4	-0/+3441
*	Run dffsr2dff in synth_xilinx	Clifford Wolf	2016-02-13	1	-0/+2
*	Added "abc -luts" option, Improved Xilinx logic mapping	Clifford Wolf	2016-02-01	1	-2/+2
*	Bugfix in Xilinx LUT mapping	Clifford Wolf	2015-10-30	1	-1/+1
*	Added examples/ top-level directory	Clifford Wolf	2015-10-13	7	-77/+0
*	Added read-enable to memory model	Clifford Wolf	2015-09-25	3	-19/+23
*	Switched to Python 3	Clifford Wolf	2015-08-22	2	-5/+2
*	Another bugfix for ice40 and xilinx brams_init make rules	Clifford Wolf	2015-08-16	2	-5/+5
*	Fixed Makefile rules for generated share files	Clifford Wolf	2015-08-16	1	-1/+7
*	Adjust makefiles to work with out-of-tree builds	Clifford Wolf	2015-08-12	1	-6/+2
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	3	-6/+6
*	Added output args to synth_ice40	Clifford Wolf	2015-05-26	1	-2/+2
*	Verific build fixes	Clifford Wolf	2015-05-17	1	-2/+2
*	Improved xilinx "bram1" test	Clifford Wolf	2015-04-09	1	-1/+2
*	Added memory_bram "make_outreg" feature	Clifford Wolf	2015-04-09	1	-0/+2
*	Xilinx DRAMS: RAM64X1D, RAM128X1D	Clifford Wolf	2015-04-09	3	-13/+67