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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 17:51:50 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 17:51:50 -0700 |
| commit | 96f00e9147967b587ee3b0118b944464b06da0b6 (patch) | |
| tree | fbd17c9ae59b72c8bc35c2c3bd6b6bbbd4b67d61 /techlibs/xilinx | |
| parent | 8f666ebac16a3730aeca4738fc1019e9e7a7e51f (diff) | |
| download | yosys-96f00e9147967b587ee3b0118b944464b06da0b6.tar.gz yosys-96f00e9147967b587ee3b0118b944464b06da0b6.tar.bz2 yosys-96f00e9147967b587ee3b0118b944464b06da0b6.zip | |
Typo
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/abc_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index 56b4fe7f9..dc5032d23 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -165,7 +165,7 @@ module RAM64X1D ( \$__ABC_LUTMUX6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO)); endmodule -module \$__ABC_RAM128X1D ( +module RAM128X1D ( output DPO, SPO, input D, input WCLK, |