| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add "-W' wire delay arg to abc9, use from synth_xilinx | Eddie Hung | 2019-06-11 | 1 | -1/+1 |
| * | Disable dist RAM boxes due to comb loop | Eddie Hung | 2019-06-11 | 1 | -2/+2 |
| * | Remove #ifndef ABC | Eddie Hung | 2019-06-11 | 1 | -4/+0 |
| * | Revert "Revert "Move ff_map back after ABC for shregmap"" | Eddie Hung | 2019-06-10 | 1 | -5/+5 |
| * | Revert "Rename shregmap -tech xilinx -> xilinx_dynamic" | Eddie Hung | 2019-06-10 | 1 | -2/+2 |
| * | Comment out muxpack (currently broken) | Eddie Hung | 2019-06-07 | 1 | -2/+2 |
| * | $__XILINX_MUX_ -> $__XILINX_SHIFTX | Eddie Hung | 2019-06-06 | 2 | -11/+11 |
| * | Fix muxcover and its techmapping | Eddie Hung | 2019-06-06 | 2 | -3/+3 |
| * | Run muxpack and muxcover in synth_xilinx | Eddie Hung | 2019-06-06 | 2 | -1/+18 |
| * | Remove abc_flop attributes for now | Eddie Hung | 2019-06-06 | 1 | -56/+10 |
| * | Update abc attributes on FD*E_1 | Eddie Hung | 2019-06-05 | 1 | -6/+26 |
| * | Cleanup | Eddie Hung | 2019-06-05 | 2 | -17/+0 |
| * | Call shregmap -tech xilinx_static | Eddie Hung | 2019-06-05 | 1 | -1/+1 |
| * | Revert "Move ff_map back after ABC for shregmap" | Eddie Hung | 2019-06-05 | 1 | -4/+4 |
| * | Rename shregmap -tech xilinx -> xilinx_dynamic | Eddie Hung | 2019-06-04 | 1 | -2/+2 |
| * | Add space between -D and _ABC | Eddie Hung | 2019-06-04 | 1 | -2/+2 |
| * | Add (* abc_flop_q *) to brams_bb.v | Eddie Hung | 2019-06-04 | 1 | -8/+8 |
| * | Fix name clash | Eddie Hung | 2019-06-04 | 1 | -11/+11 |
| * | Add mux_map.v for wide mux | Eddie Hung | 2019-06-04 | 4 | -30/+82 |
| * | Move ff_map back after ABC for shregmap | Eddie Hung | 2019-06-03 | 1 | -4/+4 |
| * | Respect -nocarry | Eddie Hung | 2019-06-03 | 1 | -1/+3 |
| * | Fix pmux2shiftx logic | Eddie Hung | 2019-06-03 | 1 | -1/+1 |
| * | Merge mistake | Eddie Hung | 2019-06-03 | 1 | -14/+6 |
| * | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-06-03 | 1 | -1/+5 |
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| | * | Remove extra newline | Eddie Hung | 2019-06-03 | 1 | -1/+0 |
| | * | Execute techmap and arith_map simultaneously | Eddie Hung | 2019-06-03 | 1 | -6/+6 |
| * | | Typo | Eddie Hung | 2019-06-03 | 1 | -1/+1 |
| * | | IS_C_INVERTED | Eddie Hung | 2019-06-03 | 1 | -4/+4 |
| * | | Fix `ifndef | Eddie Hung | 2019-06-03 | 1 | -1/+1 |
| * | | Add flops as blackboxes | Eddie Hung | 2019-05-31 | 2 | -0/+27 |
| * | | Add FD*E_1 -> FD*E techmap rules | Eddie Hung | 2019-05-31 | 1 | -5/+31 |
| * | | Techmap flops before ABC again | Eddie Hung | 2019-05-31 | 1 | -4/+4 |
| * | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-05-31 | 1 | -0/+1 |
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| | * \ | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-22 | 6 | -36/+222 |
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| | * \ \ | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-22 | 1 | -8/+10 |
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| | * \ \ \ | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-20 | 2 | -10/+12 |
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| * | | | | | | Remove whitebox attribute from DRAMs for now | Eddie Hung | 2019-05-30 | 1 | -2/+2 |
| * | | | | | | Carry in/out to be the last input/output for chains to be preserved | Eddie Hung | 2019-05-30 | 2 | -12/+15 |
| * | | | | | | Some more realistic delays... | Eddie Hung | 2019-05-29 | 1 | -7/+7 |
| * | | | | | | Typo | Eddie Hung | 2019-05-28 | 1 | -1/+1 |
| * | | | | | | Make MUXF{7,8} and CARRY4 whitebox | Eddie Hung | 2019-05-27 | 1 | -3/+3 |
| * | | | | | | Re-enable lib_whitebox | Eddie Hung | 2019-05-27 | 1 | -5/+5 |
| * | | | | | | Blackboxes | Eddie Hung | 2019-05-26 | 2 | -10/+10 |
| * | | | | | | Muck about with LUT delays some more | Eddie Hung | 2019-05-26 | 1 | -5/+5 |
| * | | | | | | Try new LUT delays | Eddie Hung | 2019-05-24 | 1 | -8/+11 |
| * | | | | | | Transpose CARRY4 delays | Eddie Hung | 2019-05-24 | 1 | -10/+8 |
| * | | | | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-23 | 1 | -0/+4 |
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| | * | | | | | Add "min bits" and "min wports" to xilinx dram rules | Eddie Hung | 2019-05-23 | 1 | -0/+4 |
| * | | | | | | Add whitebox support to DRAM | Eddie Hung | 2019-05-23 | 5 | -24/+26 |
| * | | | | | | shift register inference before mux | Eddie Hung | 2019-05-22 | 1 | -3/+3 |
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index : iCE40/yosys | |
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