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* Merge pull request #1601 from YosysHQ/eddie/synth_retimeEddie Hung2020-01-021-3/+3
|\ | | | | "abc -dff" to no longer retime by default
| * Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-301-1/+1
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| * Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-2/+2
| | | | | | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.
* | ifdef __ICARUS__ -> ifndef YOSYSEddie Hung2020-01-011-6/+6
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* | Update timings for Xilinx S7 cellsEddie Hung2019-12-301-15/+35
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* | Merge remote-tracking branch 'origin/master' into iopad_defaultMiodrag Milanovic2019-12-288-10/+368
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| * Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgenMarcin Kościelnicki2019-12-253-3/+6
| |\ | | | | | | xilinx_dsp: Initial DSP48A/DSP48A1 support.
| | * xilinx_dsp: Initial DSP48A/DSP48A1 support.Marcin Kościelnicki2019-12-223-3/+6
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| * | xilinx: Test our DSP48A/DSP48A1 simulation models.Marcin Kościelnicki2019-12-235-7/+362
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* | Addressed review commentsMiodrag Milanovic2019-12-211-2/+3
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* | iopad no op for compatibility with old scriptsMiodrag Milanovic2019-12-211-0/+3
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* | Make iopad option default for all xilinx flowsMiodrag Milanovic2019-12-211-14/+5
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* Add abc9_arrival times for RAM{32,64}MEddie Hung2019-12-201-24/+10
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* Add RAM{32,64}M to abc9_map.vEddie Hung2019-12-201-0/+78
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* Revert "Optimise write_xaiger"Eddie Hung2019-12-201-5/+0
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* Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-191-0/+5
|\ | | | | Optimise write_xaiger
| * techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaigerEddie Hung2019-12-061-0/+5
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* | xilinx: Add simulation models for remaining CLB primitives.Marcin Kościelnicki2019-12-193-156/+210
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* | xilinx_dffopt: Keep order of LUT inputs.Marcin Kościelnicki2019-12-191-16/+30
| | | | | | | | See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549
* | xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-186-22/+389
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* | xilinx: Improve flip-flop handling.Marcin Kościelnicki2019-12-184-38/+228
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data.
* | Merge pull request #1574 from YosysHQ/eddie/xilinx_lutramEddie Hung2019-12-163-12/+301
|\ \ | | | | | | xilinx: add LUTRAM rules for RAM32M, RAM64M
| * \ Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into ↵Eddie Hung2019-12-161-2/+8
| |\ \ | | | | | | | | | | | | eddie/xilinx_lutram
| | * | Populate DID/DOD even if unusedEddie Hung2019-12-161-2/+8
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| * | | Rename *RAM{32,64}M rules to RAM{32X2,64X1}QEddie Hung2019-12-162-6/+6
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| * | Disable RAM16X1D match rule; carry-over from LUT4 archesEddie Hung2019-12-131-6/+9
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| * | RAM64M8 to also have [5:0] for addressEddie Hung2019-12-131-8/+8
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| * | Add RAM32X6SDP and RAM64X3SDP modesEddie Hung2019-12-122-8/+120
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| * | Fix RAM64M model to have 6 bit address busEddie Hung2019-12-121-4/+4
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| * | Add memory rules for RAM16X1D, RAM32M, RAM64MEddie Hung2019-12-122-0/+168
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* | | Add unconditional match blocks for force RAMEddie Hung2019-12-161-4/+36
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* | | Update xc7/xcu bram rulesEddie Hung2019-12-161-8/+4
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* | | Removing fixed attribute value to !ramstyle rulesDiego H2019-12-151-4/+4
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* | | Merging attribute rules into a single match block; Adding testsDiego H2019-12-151-18/+12
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* | | Refactoring memory attribute matching based on IEEE 1364.1 and Tool specificDiego H2019-12-131-0/+19
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* | | Merge pull request #1533 from dh73/bram_xilinxEddie Hung2019-12-131-6/+9
|\ \ \ | |/ / |/| | Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1
| * | Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.Diego H2019-12-121-5/+5
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| * | Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1Diego H2019-12-121-2/+2
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| * | Merge https://github.com/YosysHQ/yosys into bram_xilinxDiego H2019-12-125-633/+868
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| * | Adjusting Vivado's BRAM min bits threshold for RAMB18E1Diego H2019-11-271-2/+5
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* | | abc9_map.v: fix Xilinx LUTRAMEddie Hung2019-12-121-6/+6
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* | xilinx: Add tristate buffer mapping. (#1528)Marcin Kościelnicki2019-12-042-9/+16
| | | | | | Fixes #1225.
* | xilinx: Add models for LUTRAM cells. (#1537)Marcin Kościelnicki2019-12-043-624/+831
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* | xilinx: Add missing blackbox cell for BUFPLL.Marcin Kościelnicki2019-11-292-0/+21
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* xilinx: Add simulation models for IOBUF and OBUFT.Marcin Kościelnicki2019-11-263-25/+30
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* clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-1/+5
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* xilinx: Use INV instead of LUT1 when applicableMarcin Kościelnicki2019-11-251-2/+6
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* xilinx: Add simulation models for MULT18X18* and DSP48A*.Marcin Kościelnicki2019-11-193-132/+516
| | | | | | | | | This adds simulation models for the following primitives: - MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3) - MULT18X18SIO (Spartan 3E, Spartan 3A) - DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1 - DSP48A1 (Spartan 6)
* synth_xilinx: Merge blackbox primitive libraries.Marcin Kościelnicki2019-11-0611-23234/+29820
| | | | | | | | | | | | | | | | | | | | | | | | | First, there are no longer separate cell libraries for xc6s/xc7/xcu. Manually instantiating a primitive for a "wrong" family will result in yosys passing it straight through to the output, and it will be either upgraded or rejected by the P&R tool. Second, the blackbox library is expanded to cover many more families: everything from Spartan 3 up is included. Primitives for Virtex and Virtex 2 are listed in the Python file as well if we ever want to include them, but that would require having two different ISE versions (10.1 and 14.7) available when running cells_xtra.py, and so is probably more trouble than it's worth. Third, the blockram blackboxes are no longer in separate files — there is no practical reason to do so (from synthesis PoV, they are no different from any other cells_xtra blackbox), and they needlessly complicated the flow (among other things, merging them allows the user to use eg. Series 7 primitives and have them auto-upgraded to Ultrascale). Last, since xc5v logic synthesis appears to work reasonably well (the only major problem is lack of blockram inference support), xc5v is now an accepted setting for the -family option.
* xilinx: Add URAM288 mapping for xcupDavid Shah2019-10-235-2/+92
| | | | Signed-off-by: David Shah <dave@ds0.me>
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