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Commit message (
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Author
Age
Files
Lines
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Restore abc9 -keepff
Eddie Hung
2020-01-01
2
-86
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+6
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Re-arrange FD order
Eddie Hung
2019-12-31
3
-182
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+182
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Cleanup xilinx boxes
Eddie Hung
2019-12-31
2
-391
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+425
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Update abc9_xc7.box comments
Eddie Hung
2019-12-31
1
-18
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+18
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FDCE ports to be alphabetical
Eddie Hung
2019-12-31
1
-3
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+3
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Fix attributes on $__ABC9_ASYNC[01] whitebox
Eddie Hung
2019-12-31
1
-2
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+2
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Fix incorrect $__ABC9_ASYNC[01] box
Eddie Hung
2019-12-31
1
-2
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+2
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Do not offset FD* box timings due to -46ps Tsu
Eddie Hung
2019-12-30
1
-12
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+21
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-30
8
-21
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+374
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Merge remote-tracking branch 'origin/master' into iopad_default
Miodrag Milanovic
2019-12-28
8
-10
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+368
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Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen
Marcin Kościelnicki
2019-12-25
3
-3
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+6
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xilinx_dsp: Initial DSP48A/DSP48A1 support.
Marcin Kościelnicki
2019-12-22
3
-3
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+6
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xilinx: Test our DSP48A/DSP48A1 simulation models.
Marcin Kościelnicki
2019-12-23
5
-7
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+362
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Addressed review comments
Miodrag Milanovic
2019-12-21
1
-2
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+3
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iopad no op for compatibility with old scripts
Miodrag Milanovic
2019-12-21
1
-0
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+3
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Make iopad option default for all xilinx flows
Miodrag Milanovic
2019-12-21
1
-14
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+5
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Tidy up abc9_map.v
Eddie Hung
2019-12-30
1
-103
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+103
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Add "synth_xilinx -dff" option, cleanup abc9
Eddie Hung
2019-12-30
2
-2
/
+98
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-20
1
-24
/
+10
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Add abc9_arrival times for RAM{32,64}M
Eddie Hung
2019-12-20
1
-24
/
+10
*
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-20
4
-172
/
+240
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Add RAM{32,64}M to abc9_map.v
Eddie Hung
2019-12-20
1
-0
/
+78
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Revert "Optimise write_xaiger"
Eddie Hung
2019-12-20
1
-5
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+0
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Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
Eddie Hung
2019-12-19
1
-0
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+5
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techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger
Eddie Hung
2019-12-06
1
-0
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+5
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xilinx: Add simulation models for remaining CLB primitives.
Marcin Kościelnicki
2019-12-19
3
-156
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+210
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xilinx_dffopt: Keep order of LUT inputs.
Marcin Kościelnicki
2019-12-19
1
-16
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+30
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Add RAM{32,64}M to abc9_map.v
Eddie Hung
2019-12-19
1
-0
/
+78
*
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Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t
Eddie Hung
2019-12-19
5
-36
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+55
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-19
12
-77
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+967
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xilinx: Add xilinx_dffopt pass (#1557)
Marcin Kościelnicki
2019-12-18
6
-22
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+389
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xilinx: Improve flip-flop handling.
Marcin Kościelnicki
2019-12-18
4
-38
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+228
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Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram
Eddie Hung
2019-12-16
3
-12
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+301
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Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xil...
Eddie Hung
2019-12-16
1
-2
/
+8
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Populate DID/DOD even if unused
Eddie Hung
2019-12-16
1
-2
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+8
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Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q
Eddie Hung
2019-12-16
2
-6
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+6
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Disable RAM16X1D match rule; carry-over from LUT4 arches
Eddie Hung
2019-12-13
1
-6
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+9
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RAM64M8 to also have [5:0] for address
Eddie Hung
2019-12-13
1
-8
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+8
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Add RAM32X6SDP and RAM64X3SDP modes
Eddie Hung
2019-12-12
2
-8
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+120
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Fix RAM64M model to have 6 bit address bus
Eddie Hung
2019-12-12
1
-4
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+4
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Add memory rules for RAM16X1D, RAM32M, RAM64M
Eddie Hung
2019-12-12
2
-0
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+168
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*
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Add unconditional match blocks for force RAM
Eddie Hung
2019-12-16
1
-4
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+36
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Update xc7/xcu bram rules
Eddie Hung
2019-12-16
1
-8
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+4
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Removing fixed attribute value to !ramstyle rules
Diego H
2019-12-15
1
-4
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+4
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Merging attribute rules into a single match block; Adding tests
Diego H
2019-12-15
1
-18
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+12
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Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific
Diego H
2019-12-13
1
-0
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+19
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Merge pull request #1533 from dh73/bram_xilinx
Eddie Hung
2019-12-13
1
-6
/
+9
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Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.
Diego H
2019-12-12
1
-5
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+5
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Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1
Diego H
2019-12-12
1
-2
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+2
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Merge https://github.com/YosysHQ/yosys into bram_xilinx
Diego H
2019-12-12
5
-633
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+868
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