index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
techlibs
/
xilinx
Commit message (
Expand
)
Author
Age
Files
Lines
*
Restore abc9 -keepff
Eddie Hung
2020-01-01
2
-86
/
+6
*
Re-arrange FD order
Eddie Hung
2019-12-31
3
-182
/
+182
*
Cleanup xilinx boxes
Eddie Hung
2019-12-31
2
-391
/
+425
*
Update abc9_xc7.box comments
Eddie Hung
2019-12-31
1
-18
/
+18
*
FDCE ports to be alphabetical
Eddie Hung
2019-12-31
1
-3
/
+3
*
Fix attributes on $__ABC9_ASYNC[01] whitebox
Eddie Hung
2019-12-31
1
-2
/
+2
*
Fix incorrect $__ABC9_ASYNC[01] box
Eddie Hung
2019-12-31
1
-2
/
+2
*
Do not offset FD* box timings due to -46ps Tsu
Eddie Hung
2019-12-30
1
-12
/
+21
*
Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-30
8
-21
/
+374
|
\
|
*
Merge remote-tracking branch 'origin/master' into iopad_default
Miodrag Milanovic
2019-12-28
8
-10
/
+368
|
|
\
|
|
*
Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen
Marcin Kościelnicki
2019-12-25
3
-3
/
+6
|
|
|
\
|
|
|
*
xilinx_dsp: Initial DSP48A/DSP48A1 support.
Marcin Kościelnicki
2019-12-22
3
-3
/
+6
|
|
*
|
xilinx: Test our DSP48A/DSP48A1 simulation models.
Marcin Kościelnicki
2019-12-23
5
-7
/
+362
|
|
|
/
|
*
|
Addressed review comments
Miodrag Milanovic
2019-12-21
1
-2
/
+3
|
*
|
iopad no op for compatibility with old scripts
Miodrag Milanovic
2019-12-21
1
-0
/
+3
|
*
|
Make iopad option default for all xilinx flows
Miodrag Milanovic
2019-12-21
1
-14
/
+5
|
|
/
*
|
Tidy up abc9_map.v
Eddie Hung
2019-12-30
1
-103
/
+103
*
|
Add "synth_xilinx -dff" option, cleanup abc9
Eddie Hung
2019-12-30
2
-2
/
+98
*
|
Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-20
1
-24
/
+10
|
\
|
|
*
Add abc9_arrival times for RAM{32,64}M
Eddie Hung
2019-12-20
1
-24
/
+10
*
|
Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-20
4
-172
/
+240
|
\
|
|
*
Add RAM{32,64}M to abc9_map.v
Eddie Hung
2019-12-20
1
-0
/
+78
|
*
Revert "Optimise write_xaiger"
Eddie Hung
2019-12-20
1
-5
/
+0
|
*
Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
Eddie Hung
2019-12-19
1
-0
/
+5
|
|
\
|
|
*
techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger
Eddie Hung
2019-12-06
1
-0
/
+5
|
*
|
xilinx: Add simulation models for remaining CLB primitives.
Marcin Kościelnicki
2019-12-19
3
-156
/
+210
|
*
|
xilinx_dffopt: Keep order of LUT inputs.
Marcin Kościelnicki
2019-12-19
1
-16
/
+30
*
|
|
Add RAM{32,64}M to abc9_map.v
Eddie Hung
2019-12-19
1
-0
/
+78
*
|
|
Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t
Eddie Hung
2019-12-19
5
-36
/
+55
*
|
|
Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-19
12
-77
/
+967
|
\
|
|
|
*
|
xilinx: Add xilinx_dffopt pass (#1557)
Marcin Kościelnicki
2019-12-18
6
-22
/
+389
|
*
|
xilinx: Improve flip-flop handling.
Marcin Kościelnicki
2019-12-18
4
-38
/
+228
|
*
|
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram
Eddie Hung
2019-12-16
3
-12
/
+301
|
|
\
\
|
|
*
\
Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xil...
Eddie Hung
2019-12-16
1
-2
/
+8
|
|
|
\
\
|
|
|
*
|
Populate DID/DOD even if unused
Eddie Hung
2019-12-16
1
-2
/
+8
|
|
*
|
|
Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q
Eddie Hung
2019-12-16
2
-6
/
+6
|
|
|
/
/
|
|
*
|
Disable RAM16X1D match rule; carry-over from LUT4 arches
Eddie Hung
2019-12-13
1
-6
/
+9
|
|
*
|
RAM64M8 to also have [5:0] for address
Eddie Hung
2019-12-13
1
-8
/
+8
|
|
*
|
Add RAM32X6SDP and RAM64X3SDP modes
Eddie Hung
2019-12-12
2
-8
/
+120
|
|
*
|
Fix RAM64M model to have 6 bit address bus
Eddie Hung
2019-12-12
1
-4
/
+4
|
|
*
|
Add memory rules for RAM16X1D, RAM32M, RAM64M
Eddie Hung
2019-12-12
2
-0
/
+168
|
*
|
|
Add unconditional match blocks for force RAM
Eddie Hung
2019-12-16
1
-4
/
+36
|
*
|
|
Update xc7/xcu bram rules
Eddie Hung
2019-12-16
1
-8
/
+4
|
*
|
|
Removing fixed attribute value to !ramstyle rules
Diego H
2019-12-15
1
-4
/
+4
|
*
|
|
Merging attribute rules into a single match block; Adding tests
Diego H
2019-12-15
1
-18
/
+12
|
*
|
|
Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific
Diego H
2019-12-13
1
-0
/
+19
|
*
|
|
Merge pull request #1533 from dh73/bram_xilinx
Eddie Hung
2019-12-13
1
-6
/
+9
|
|
\
\
\
|
|
|
/
/
|
|
/
|
|
|
|
*
|
Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.
Diego H
2019-12-12
1
-5
/
+5
|
|
*
|
Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1
Diego H
2019-12-12
1
-2
/
+2
|
|
*
|
Merge https://github.com/YosysHQ/yosys into bram_xilinx
Diego H
2019-12-12
5
-633
/
+868
|
|
|
\
|
[next]