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xilinx
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xc7_xcu_brams.txt
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Author
Age
Files
Lines
*
xilinx: Use `memory_libmap` pass.
Marcelina Kościelnicka
2022-05-18
1
-151
/
+0
|
*
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
Marcin Kościelnicki
2020-02-07
1
-0
/
+2
|
*
Add unconditional match blocks for force RAM
Eddie Hung
2019-12-16
1
-4
/
+36
|
*
Update xc7/xcu bram rules
Eddie Hung
2019-12-16
1
-8
/
+4
|
*
Removing fixed attribute value to !ramstyle rules
Diego H
2019-12-15
1
-4
/
+4
|
*
Merging attribute rules into a single match block; Adding tests
Diego H
2019-12-15
1
-18
/
+12
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*
Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific
Diego H
2019-12-13
1
-0
/
+19
|
*
Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.
Diego H
2019-12-12
1
-5
/
+5
|
*
Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1
Diego H
2019-12-12
1
-2
/
+2
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*
Adjusting Vivado's BRAM min bits threshold for RAMB18E1
Diego H
2019-11-27
1
-2
/
+5
|
*
xilinx: Add support for UltraScale[+] BRAM mapping
David Shah
2019-10-23
1
-0
/
+105
Signed-off-by: David Shah <dave@ds0.me>
