| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | xilinx: Use dfflegalize. | Marcelina Kościelnicka | 2020-07-09 | 1 | -178/+0 |
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| * | Update dff2dffe, dff2dffs, zinit to new FF types. | Marcelina Kościelnicka | 2020-06-23 | 1 | -12/+12 |
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| * | xilinx: Improve flip-flop handling. | Marcin Kościelnicki | 2019-12-18 | 1 | -16/+78 |
| | | | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data. | ||||
| * | synth_xilinx: Support latches, remove used-up FF init values. | Marcin Kościelnicki | 2019-09-30 | 1 | -1/+39 |
| | | | | | Fixes #1387. | ||||
| * | synth_xilinx: Support init values on Spartan 6 flip-flops properly. | Marcin Kościelnicki | 2019-09-07 | 1 | -0/+78 |
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index : iCE40/yosys | |
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