| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -8/+8 |
| * | Use extractinv for synth_xilinx -ise | Marcin Kościelnicki | 2019-09-19 | 1 | -0/+16 |
| * | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-28 | 1 | -0/+4 |
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| | * | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 1 | -2/+4 |
| | * | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 1 | -0/+2 |
| * | | Put attributes above port | Eddie Hung | 2019-08-23 | 1 | -8/+16 |
| * | | Add BRAM arrival times | Eddie Hung | 2019-08-19 | 1 | -8/+10 |
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| * | synth_xilinx: Initial Spartan 6 block RAM inference support. | Marcin Kościelnicki | 2019-07-11 | 1 | -0/+319 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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