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| author | Marcin Kościelnicki <koriakin@0x04.net> | 2019-08-28 15:28:01 +0000 |
|---|---|---|
| committer | Marcin Kościelnicki <koriakin@0x04.net> | 2019-09-19 04:02:48 +0200 |
| commit | 13fa873f11c8332a10c1dda9e42c62b20e93c6b3 (patch) | |
| tree | 98edcd08223ee6b4d89a9e9919b08afc54c48dfd /techlibs/xilinx/xc7_brams_bb.v | |
| parent | c9f9518de4af34b2539d230c0894b04d174b755d (diff) | |
| download | yosys-13fa873f11c8332a10c1dda9e42c62b20e93c6b3.tar.gz yosys-13fa873f11c8332a10c1dda9e42c62b20e93c6b3.tar.bz2 yosys-13fa873f11c8332a10c1dda9e42c62b20e93c6b3.zip | |
Use extractinv for synth_xilinx -ise
Diffstat (limited to 'techlibs/xilinx/xc7_brams_bb.v')
| -rw-r--r-- | techlibs/xilinx/xc7_brams_bb.v | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/techlibs/xilinx/xc7_brams_bb.v b/techlibs/xilinx/xc7_brams_bb.v index 5b40a457d..a28ba5b14 100644 --- a/techlibs/xilinx/xc7_brams_bb.v +++ b/techlibs/xilinx/xc7_brams_bb.v @@ -2,16 +2,24 @@ module RAMB18E1 ( (* clkbuf_sink *) + (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) input CLKARDCLK, (* clkbuf_sink *) + (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) input CLKBWRCLK, + (* invertible_pin = "IS_ENARDEN_INVERTED" *) input ENARDEN, + (* invertible_pin = "IS_ENBWREN_INVERTED" *) input ENBWREN, input REGCEAREGCE, input REGCEB, + (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) input RSTRAMARSTRAM, + (* invertible_pin = "IS_RSTRAMB_INVERTED" *) input RSTRAMB, + (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) input RSTREGARSTREG, + (* invertible_pin = "IS_RSTREGB_INVERTED" *) input RSTREGB, input [13:0] ADDRARDADDR, @@ -132,16 +140,24 @@ endmodule module RAMB36E1 ( (* clkbuf_sink *) + (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) input CLKARDCLK, (* clkbuf_sink *) + (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) input CLKBWRCLK, + (* invertible_pin = "IS_ENARDEN_INVERTED" *) input ENARDEN, + (* invertible_pin = "IS_ENBWREN_INVERTED" *) input ENBWREN, input REGCEAREGCE, input REGCEB, + (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) input RSTRAMARSTRAM, + (* invertible_pin = "IS_RSTRAMB_INVERTED" *) input RSTRAMB, + (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) input RSTREGARSTREG, + (* invertible_pin = "IS_RSTREGB_INVERTED" *) input RSTREGB, input [15:0] ADDRARDADDR, |