iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	xilinx: Add simulation models for remaining CLB primitives.	Marcin Kościelnicki	2019-12-19	1	-13/+13
*	xilinx: Add xilinx_dffopt pass (#1557)	Marcin Kościelnicki	2019-12-18	1	-1/+1
*	xilinx: Add models for LUTRAM cells. (#1537)	Marcin Kościelnicki	2019-12-04	1	-34/+34
*	xilinx: Add missing blackbox cell for BUFPLL.	Marcin Kościelnicki	2019-11-29	1	-0/+1
*	xilinx: Add simulation models for IOBUF and OBUFT.	Marcin Kościelnicki	2019-11-26	1	-2/+2
*	xilinx: Add simulation models for MULT18X18* and DSP48A*.	Marcin Kościelnicki	2019-11-19	1	-5/+5
*	synth_xilinx: Merge blackbox primitive libraries.	Marcin Kościelnicki	2019-11-06	1	-488/+477
*	xilinx: Add support for UltraScale[+] BRAM mapping	David Shah	2019-10-23	1	-8/+14
*	xilinx: Add simulation model for IBUFG.	Marcin Kościelnicki	2019-10-10	1	-3/+3
*	Remove DSP48E1 from *_cells_xtra.v	Eddie Hung	2019-10-04	1	-2/+2
*	Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}	Eddie Hung	2019-09-30	1	-2/+2
*	Use extractinv for synth_xilinx -ise	Marcin Kościelnicki	2019-09-19	1	-3/+20
*	xilinx: Make blackbox library family-dependent.	Marcin Kościelnicki	2019-09-15	1	-45/+479
*	move attributes to wires	Marcin Kościelnicki	2019-08-13	1	-0/+257