iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Typo	Eddie Hung	2019-06-03	1	-1/+1
*	Fix `ifndef	Eddie Hung	2019-06-03	1	-1/+1
*	Add FDE_1 -> FDE techmap rules	Eddie Hung	2019-05-31	1	-5/+31
*	Remove whitebox attribute from DRAMs for now	Eddie Hung	2019-05-30	1	-2/+2
*	Carry in/out to be the last input/output for chains to be preserved	Eddie Hung	2019-05-30	1	-2/+2
*	Re-enable lib_whitebox	Eddie Hung	2019-05-27	1	-5/+5
*	Blackboxes	Eddie Hung	2019-05-26	1	-5/+5
*	Add whitebox support to DRAM	Eddie Hung	2019-05-23	1	-2/+8
*	Instead of MUXCY/XORCY use CARRY4 (with timing)	Eddie Hung	2019-05-21	1	-2/+1
*	Cleanup, call pmux2shiftx even without -nosrl	Eddie Hung	2019-04-22	1	-12/+16
*	Merge remote-tracking branch 'origin' into xc7srl	Eddie Hung	2019-04-20	1	-0/+57
\|\
\| *	Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.	Keith Rothman	2019-04-12	1	-11/+11
\| *	Fix LUT6_2 definition.	Keith Rothman	2019-04-09	1	-3/+3
\| *	Add additional cells sim models for core 7-series primatives.	Keith Rothman	2019-04-09	1	-0/+57
* \|	Merge remote-tracking branch 'origin/master' into xc7srl	Eddie Hung	2019-03-14	1	-0/+65
\|\\|
\| *	Revert FF models to include IS_x_INVERTED parameters.	Keith Rothman	2019-03-01	1	-6/+34
\| *	Changes required for VPR place and route synth_xilinx.	Keith Rothman	2019-03-01	1	-33/+70
* \|	Add SRL16 and SRL32 sim models	Eddie Hung	2019-02-28	1	-0/+39
\|/
*	Add Xilinx RAM64X1D and RAM128X1D simulation models	Clifford Wolf	2018-03-07	1	-0/+30
*	Disabled (unused) Xilinx tristate buffers	Clifford Wolf	2015-02-04	1	-6/+6
*	Added Xilinx example for Basys3 board	Clifford Wolf	2015-02-01	1	-1/+5
*	Fixed xilinx FDSE sim model	Clifford Wolf	2015-01-24	1	-2/+2
*	Added MUXCY and XORCY support to synth_xilinx	Clifford Wolf	2015-01-17	1	-0/+4
*	Added FF cells to xilinx/cells_sim.v	Clifford Wolf	2015-01-16	1	-116/+116
*	added minimalistic xilinx sim models	Clifford Wolf	2015-01-08	1	-0/+150