iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-04-22	1	-10/+19
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\| *	ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware exp...	Luke Wren	2019-04-21	1	-10/+19
* \|	Convert to use #945	Eddie Hung	2019-04-21	2	-9/+3
* \|	ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL set	Eddie Hung	2019-04-19	2	-4/+7
* \|	Make SB_DFF whitebox	Eddie Hung	2019-04-19	3	-3/+3
* \|	Fix SB_DFF comb model	Eddie Hung	2019-04-18	2	-3/+3
* \|	Missing close bracket	Eddie Hung	2019-04-18	1	-1/+1
* \|	Annotate SB_DFF* with abc_flop and abc_box_id	Eddie Hung	2019-04-18	1	-22/+49
* \|	Add SB_DFF* to boxes	Eddie Hung	2019-04-18	3	-6/+306
* \|	Use new -wb flag for ABC flow	Eddie Hung	2019-04-18	3	-19/+5
* \|	Also update Makefile.inc	Eddie Hung	2019-04-18	1	-7/+6
* \|	Make SB_LUT4 a blackbox	Eddie Hung	2019-04-18	3	-3/+3
* \|	Fix rename	Eddie Hung	2019-04-18	1	-0/+0
* \|	Rename to abc_*.{box,lut}	Eddie Hung	2019-04-18	6	-0/+0
* \|	Update Makefile.inc too	Eddie Hung	2019-04-17	1	-4/+6
* \|	Reduce to three devices: hx, lp, u	Eddie Hung	2019-04-17	7	-4/+23
* \|	Add up5k timings	Eddie Hung	2019-04-17	2	-0/+19
* \|	Update error message	Eddie Hung	2019-04-17	1	-1/+1
* \|	Add "-device" argument to synth_ice40	Eddie Hung	2019-04-17	4	-7/+20
* \|	Missing abc_flop_q attribute on SPRAM	Eddie Hung	2019-04-17	1	-1/+1
* \|	Map to SB_LUT4 from fastest input first	Eddie Hung	2019-04-17	1	-7/+11
* \|	Mark seq output ports with "abc_flop_q" attr	Eddie Hung	2019-04-17	1	-24/+24
* \|	Also update Makefile.inc	Eddie Hung	2019-04-17	1	-3/+3
* \|	synth_ice40 to use renamed files	Eddie Hung	2019-04-17	1	-2/+2
* \|	Rename to abc.*	Eddie Hung	2019-04-17	3	-0/+0
* \|	Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues"	Eddie Hung	2019-04-17	7	-102/+35
* \|	Try using an ICE40_CARRY_LUT primitive to avoid ABC issues	Eddie Hung	2019-04-17	7	-35/+102
* \|	Fix spacing	Eddie Hung	2019-04-17	1	-5/+5
* \|	Add SB_LUT4 to box library	Eddie Hung	2019-04-16	3	-0/+16
* \|	Add ice40 box files	Eddie Hung	2019-04-16	6	-1/+27
* \|	Merge branch 'master' into xaig	Eddie Hung	2019-04-08	5	-42/+198
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\| *	Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes	Clifford Wolf	2019-03-12	1	-19/+0
\| *	Fix typo in ice40_braminit help msg	Clifford Wolf	2019-03-09	1	-1/+1
\| *	Merge pull request #859 from smunaut/ice40_braminit	Clifford Wolf	2019-03-09	4	-37/+212
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\| \| *	ice40: Run ice40_braminit pass by default	Sylvain Munaut	2019-03-08	1	-0/+1
\| \| *	ice40: Add ice40_braminit pass to allow initialization of BRAM from file	Sylvain Munaut	2019-03-08	3	-37/+211
\| * \|	ice40: use 2 bits for READ/WRITE MODE for SB_RAM map	Elms	2019-02-28	1	-2/+2
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* \|	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-02-26	1	-1/+1
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\| *	Merge pull request #740 from daveshah1/improve_dress	Clifford Wolf	2019-02-22	1	-1/+1
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\| \| *	ice40: Use abc -dress in synth_ice40	David Shah	2019-02-06	1	-1/+1
* \| \|	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-02-21	6	-58/+667
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\| * \|	Bugfix in ice40_dsp	Clifford Wolf	2019-02-21	2	-20/+33
\| * \|	Add ice40 test_dsp_map test case generator	Clifford Wolf	2019-02-20	2	-0/+99
\| * \|	Add "synth_ice40 -dsp"	Clifford Wolf	2019-02-20	1	-3/+27
\| * \|	Improve iCE40 SB_MAC16 model	Clifford Wolf	2019-02-20	5	-121/+179
\| * \|	Add first draft of functional SB_MAC16 model	Clifford Wolf	2019-02-19	4	-53/+467
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* /	synth_ice40 to have new -abc9 arg	Eddie Hung	2019-02-14	1	-4/+12
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*	Merge pull request #772 from whitequark/synth_lut	Clifford Wolf	2019-01-02	1	-1/+1
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\| *	synth_ice40: use 4-LUT coarse synthesis mode.	whitequark	2019-01-02	1	-1/+1
* \|	Fix typographical and grammatical errors and inconsistencies.	whitequark	2019-01-02	1	-1/+1
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