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path: root/techlibs/ice40/cells_sim.v
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* Remove trailing comma from SB_IO_OD port listGraham Edgecombe2017-12-101-1/+1
* Add remaining UltraPlus cells to ice40 techlibDavid Shah2017-11-281-0/+263
* Remove unnecessary keep attributesDavid Shah2017-11-181-5/+5
* Add some UltraPlus cells to ice40 techlibDavid Shah2017-11-161-0/+103
* Work around DDR dout sim glitches in ice40 SB_IO sim modelClifford Wolf2016-02-071-1/+7
* Merge pull request #108 from cseed/masterClifford Wolf2015-12-071-1/+3
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| * Added LO to ICESTORM_LC for LUT cascade route.Cotton Seed2015-12-061-1/+3
* | Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handlingClifford Wolf2015-11-061-2/+2
* | Fixed ice40 handling of negclk RAM40Clifford Wolf2015-09-101-8/+8
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* Improved handling of "keep" attributes in hierarchical designs in opt_cleanClifford Wolf2015-08-121-2/+1
* Added iCE40 WARMBOOT cellMarcus Comstedt2015-08-061-0/+10
* Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)Clifford Wolf2015-07-271-1/+0
* iCE40 DFF sim models: init Q regs to 0Clifford Wolf2015-07-201-20/+43
* Avoid tristate warning for blackbox ice40/cells_sim.vClifford Wolf2015-07-181-0/+2
* Fixed trailing whitespacesClifford Wolf2015-07-021-2/+2
* Added iCE40 PLL cellsClifford Wolf2015-05-311-0/+168
* improved ice40 SB_IO sim modelClifford Wolf2015-05-231-16/+9
* Added ice40 SB_IO sim modelClifford Wolf2015-05-231-1/+46
* improved iCE40 SB_RAM40_4K simulation modelClifford Wolf2015-04-251-59/+83
* More iCE40 bram improvementsClifford Wolf2015-04-251-41/+61
* iCE40 bram tests and fixesClifford Wolf2015-04-241-8/+31
* iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* modelsClifford Wolf2015-04-191-13/+289
* Changed ice40 ICESTORM_CARRYCONST port nameClifford Wolf2015-04-161-2/+2
* improved ice40 dff cell mappingClifford Wolf2015-04-161-4/+4
* more cells in ice40 cell libraryClifford Wolf2015-04-141-8/+289
* Added very first version of "synth_ice40"Clifford Wolf2015-03-051-0/+12