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| author | Clifford Wolf <clifford@clifford.at> | 2015-07-02 11:14:30 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-07-02 11:14:30 +0200 |
| commit | 6c84341f22b2758181164e8d5cddd23e3589c90b (patch) | |
| tree | 0438ad9becf956e43ebf8665fee89e021b13bcdf /techlibs/ice40/cells_sim.v | |
| parent | 053058d78167f7f1ec377fddcee8b648a5ae4138 (diff) | |
| download | yosys-6c84341f22b2758181164e8d5cddd23e3589c90b.tar.gz yosys-6c84341f22b2758181164e8d5cddd23e3589c90b.tar.bz2 yosys-6c84341f22b2758181164e8d5cddd23e3589c90b.zip | |
Fixed trailing whitespaces
Diffstat (limited to 'techlibs/ice40/cells_sim.v')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 473701172..afa8a516b 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -15,7 +15,7 @@ module SB_IO ( ); parameter [5:0] PIN_TYPE = 6'b000000; parameter [0:0] PULLUP = 1'b0; - parameter [0:0] NEG_TRIGGER = 1'b0; + parameter [0:0] NEG_TRIGGER = 1'b0; parameter IO_STANDARD = "SB_LVCMOS"; reg dout, din_0, din_1; @@ -74,7 +74,7 @@ module SB_GB_IO ( ); parameter [5:0] PIN_TYPE = 6'b000000; parameter [0:0] PULLUP = 1'b0; - parameter [0:0] NEG_TRIGGER = 1'b0; + parameter [0:0] NEG_TRIGGER = 1'b0; parameter IO_STANDARD = "SB_LVCMOS"; assign GLOBAL_BUFFER_OUTPUT = PACKAGE_PIN; |