iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Add force_downto and force_upto wire attributes.	Marcelina Kościelnicka	2020-05-19	1	-0/+1
*	ice40: split out cells_map.v into ff_map.v	Eddie Hung	2020-05-14	1	-31/+0
*	xilinx/ice40/ecp5: undo permuting LUT masks in lut_map	Eddie Hung	2020-01-27	1	-7/+6
*	ice40_wrapcarry to really preserve attributes via -unwrap option	Eddie Hung	2019-12-09	1	-19/+0
*	$__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve	Eddie Hung	2019-12-03	1	-1/+1
*	Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER	Eddie Hung	2019-08-12	1	-1/+1
*	Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_ad...	Eddie Hung	2019-08-12	1	-14/+9
*	Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"	David Shah	2019-08-10	1	-9/+14
*	Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER	Eddie Hung	2019-08-07	1	-8/+5
*	Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER	Eddie Hung	2019-08-07	1	-12/+10
*	$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark	Eddie Hung	2019-07-15	1	-1/+1
*	_ABC macro will map and unmap to this new box	Eddie Hung	2019-07-12	1	-0/+24
*	Ooopsie	Eddie Hung	2019-06-03	1	-1/+1
*	Map to SB_LUT4 from fastest input first	Eddie Hung	2019-04-17	1	-7/+11
*	Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues"	Eddie Hung	2019-04-17	1	-24/+0
*	Try using an ICE40_CARRY_LUT primitive to avoid ABC issues	Eddie Hung	2019-04-17	1	-0/+24
*	Improving vpr output support.	Tim 'mithro' Ansell	2018-04-18	1	-1/+1
*	Add "synth_ice40 -vpr"	Clifford Wolf	2017-11-16	1	-0/+2
*	improved ice40 dff cell mapping	Clifford Wolf	2015-04-16	1	-3/+28
*	Added very first version of "synth_ice40"	Clifford Wolf	2015-03-05	1	-0/+32