diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 16:27:24 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 16:29:38 -0700 |
| commit | 675c1d42182b871ff4706b992eb005ed9d3d6f02 (patch) | |
| tree | e8902f35fba57c7d22af04907bef7dd1a926c006 /techlibs/ice40/cells_map.v | |
| parent | cc331cf70d9e9f7095e335fc217fd3dbbbe92a93 (diff) | |
| download | yosys-675c1d42182b871ff4706b992eb005ed9d3d6f02.tar.gz yosys-675c1d42182b871ff4706b992eb005ed9d3d6f02.tar.bz2 yosys-675c1d42182b871ff4706b992eb005ed9d3d6f02.zip | |
Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER
Diffstat (limited to 'techlibs/ice40/cells_map.v')
| -rw-r--r-- | techlibs/ice40/cells_map.v | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v index 511b7f6c6..0c10c9ac4 100644 --- a/techlibs/ice40/cells_map.v +++ b/techlibs/ice40/cells_map.v @@ -63,7 +63,8 @@ endmodule `endif `ifndef NO_ADDER -module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI); +module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3); + parameter LUT = 0; SB_CARRY carry ( .I0(A), .I1(B), @@ -72,13 +73,9 @@ module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI); ); \$lut #( .WIDTH(4), - // A[0]: 1010 1010 1010 1010 - // A[1]: 1100 1100 1100 1100 - // A[2]: 1111 0000 1111 0000 - // A[3]: 1111 1111 0000 0000 - .LUT(16'b 0110_1001_1001_0110) - ) adder ( - .A({CI,B,A,1'b0}), + .LUT(LUT) + ) lut ( + .A({I3,B,A,I0}), .Y(O) ); endmodule |