| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added $assert cell | Clifford Wolf | 2014-01-19 | 1 | -0/+15 |
| * | Fixed $lut simlib model for a wider range of tools | Clifford Wolf | 2014-01-18 | 1 | -10/+12 |
| * | More changes to simlib to make it friendlier to a wider range of tools | Clifford Wolf | 2014-01-18 | 1 | -10/+14 |
| * | Fixed a type in $mem model in simlib.v | Clifford Wolf | 2014-01-18 | 1 | -1/+1 |
| * | Added $bu0 cell to simlib.v | Clifford Wolf | 2014-01-18 | 1 | -0/+22 |
| * | Added support for non-const === and !== (for miter circuits) | Clifford Wolf | 2013-12-27 | 1 | -0/+36 |
| * | Renamed stdcells_sim.v to simcells.v and fixed blackbox.v | Clifford Wolf | 2013-11-24 | 1 | -8/+8 |
| * | Cleanups and bugfixes in response to new internal cell checker | Clifford Wolf | 2013-11-11 | 1 | -6/+7 |
| * | Added $sr, $dffsr and $dlatch cell types | Clifford Wolf | 2013-10-18 | 1 | -20/+76 |
| * | Moved common techlib files to techlibs/common | Clifford Wolf | 2013-09-15 | 1 | -0/+944 |
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index : iCE40/yosys | |
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