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| author | Clifford Wolf <clifford@clifford.at> | 2014-01-19 14:03:40 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-01-19 14:03:40 +0100 |
| commit | 1e67099b77904802880ad7c53d2cac33c6df456f (patch) | |
| tree | 87deccc08f9e4bbbc7d2448852daf68d4ba0b35e /techlibs/common/simlib.v | |
| parent | 9a1eb45c7517f224a2516ce235fd53d01d9ef908 (diff) | |
| download | yosys-1e67099b77904802880ad7c53d2cac33c6df456f.tar.gz yosys-1e67099b77904802880ad7c53d2cac33c6df456f.tar.bz2 yosys-1e67099b77904802880ad7c53d2cac33c6df456f.zip | |
Added $assert cell
Diffstat (limited to 'techlibs/common/simlib.v')
| -rw-r--r-- | techlibs/common/simlib.v | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 0e041e12e..8f354a63d 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -733,6 +733,21 @@ endmodule // -------------------------------------------------------- +module \$assert (A, EN); + +input A, EN; + +always @* begin + if (A !== 1'b1 && EN === 1'b1) begin + $display("Assertation failed!"); + $finish; + end +end + +endmodule + +// -------------------------------------------------------- + module \$sr (SET, CLR, Q); parameter WIDTH = 0; |