index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
techlibs
/
anlogic
/
synth_anlogic.cc
Commit message (
Expand
)
Author
Age
Files
Lines
*
Use C++11 final/override keywords.
whitequark
2020-06-18
1
-4
/
+4
*
Get rid of dffsr2dff.
Marcelina KoĆcielnicka
2020-04-15
1
-1
/
+0
*
synth_*: call 'opt -fast' after 'techmap'
Eddie Hung
2020-02-05
1
-0
/
+1
*
Merge pull request #1604 from whitequark/unify-ram-naming
whitequark
2020-01-02
1
-6
/
+18
|
\
|
*
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
whitequark
2020-01-01
1
-6
/
+18
*
|
Update doc that "-retime" calls abc with "-dff -D 1"
Eddie Hung
2019-12-30
1
-1
/
+1
*
|
Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""
Eddie Hung
2019-12-30
1
-1
/
+1
|
/
*
Proper arith for Anlogic and use standard pass
Miodrag Milanovic
2019-08-12
1
-1
/
+6
*
Merge pull request #755 from Icenowy/anlogic-dram-init
Clifford Wolf
2019-01-02
1
-0
/
+1
|
\
|
*
anlogic: implement DRAM initialization
Icenowy Zheng
2018-12-20
1
-0
/
+1
*
|
Merge pull request #750 from Icenowy/anlogic-ff-init
Clifford Wolf
2019-01-02
1
-0
/
+1
|
\
\
|
*
|
anlogic: set the init value of DFFs
Icenowy Zheng
2018-12-18
1
-0
/
+1
*
|
|
Fix typographical and grammatical errors and inconsistencies.
whitequark
2019-01-02
1
-1
/
+1
|
|
/
|
/
|
*
|
Anlogic: let LUT5/6 have more cost than LUT4-
Icenowy Zheng
2018-12-19
1
-1
/
+1
|
/
*
anlogic: add support for Eagle Distributed RAM
Icenowy Zheng
2018-12-17
1
-0
/
+6
*
Initial support for Anlogic FPGA
Miodrag Milanovic
2018-12-01
1
-0
/
+205