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| * | dfflegalize: Refactor, add aldff support.Marcelina Kościelnicka2021-10-271-973/+889
| * | verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-252-1/+7
| * | Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-251-1/+1
| * | Change implicit conversions from bool to Sig* to explicit.Marcelina Kościelnicka2021-10-211-4/+6
| * | extract_reduce: Refactor and fix input signal construction.Marcelina Kościelnicka2021-10-211-63/+34
| * | dfflegalize: remove redundant check for initialized dlatchPaul Annesley2021-10-171-4/+0
| * | FfData: some refactoring.Marcelina Kościelnicka2021-10-077-87/+48
| * | Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-023-4/+16
| * | zinit: Refactor to use FfData.Marcelina Kościelnicka2021-10-021-101/+38
| * | kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-025-130/+220
| * | simplemap: refactor to use FfData.Marcelina Kościelnicka2021-10-022-287/+20
| * | abc9: make re-entrant (#2993)Eddie Hung2021-09-092-9/+9
| * | abc9: holes module to instantiate cells with NEW_ID (#2992)Eddie Hung2021-09-091-1/+1
| * | abc9: replace cell type/parameters if derived type already processed (#2991)Eddie Hung2021-09-091-6/+22
| * | opt_merge: Remove and reinsert init when connecting nets.Marcelina Kościelnicka2021-08-221-3/+4
| * | opt_clean: Make the init attribute follow the FF's Q.Marcelina Kościelnicka2021-08-221-0/+24
| * | proc_prune: Make assign removal and promotion per-bit, remember promoted bits.Marcelina Kościelnicka2021-08-141-40/+25
| * | Add opt_mem_widen pass.Marcelina Kościelnicka2021-08-143-0/+110
| * | memory_share: Add -nosat and -nowiden options.Marcelina Kościelnicka2021-08-142-10/+41
| * | memory_dff: Recognize soft transparency logic.Marcelina Kościelnicka2021-08-131-7/+451
| * | Add new opt_mem_priority pass.Marcelina Kościelnicka2021-08-133-2/+114
| * | Merge pull request #2932 from YosysHQ/mwk/logger-check-expectedMiodrag Milanović2021-08-131-0/+9
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| | * | logger: Add -check-expected subcommand.Marcelina Kościelnicka2021-08-121-0/+9
| * | | memory_share: Pass addresses through sigmap_xmux everywhere.Marcelina Kościelnicka2021-08-131-20/+25
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| * | memory_dff: Recognize read ports with reset / initial value.Marcelina Kościelnicka2021-08-111-7/+0
| * | proc_memwr: Use the v2 memwr cell.Marcelina Kościelnicka2021-08-111-9/+19
| * | Add v2 memory cells.Marcelina Kościelnicka2021-08-117-10/+14
| * | kernel/mem: Introduce transparency masks.Marcelina Kościelnicka2021-08-114-70/+45
| * | Refactor common parts of SAT-using optimizations into a helper.Marcelina Kościelnicka2021-08-093-150/+40
| * | opt_merge: Use FfInitVals.Marcelina Kościelnicka2021-08-081-27/+8
| * | memory_share: Don't skip ports with EN wired to input for SAT sharing.Marcelina Kościelnicka2021-08-041-3/+1
| * | memory_bram: Move init data swizzling before other swizzling.Marcelina Kościelnicka2021-08-031-18/+18
| * | memory_bram: Some refactoringMarcelina Kościelnicka2021-08-011-196/+174
| * | proc_rmdead: use explicit pattern set when there are no wildcardsZachary Snow2021-07-291-2/+63
| * | opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-291-23/+30
| * | memory: Introduce $meminit_v2 cell, with EN input.Marcelina Kościelnicka2021-07-283-2/+3
| * | proc: Run opt_expr at the endMarcelina Kościelnicka2021-07-271-0/+11
| * | opt_expr: Propagate constants to port connections.Marcelina Kościelnicka2021-07-271-3/+22
| * | Use new read_id_num helper function elsewhere in hierarchy.ccRupert Swarbrick2021-07-201-5/+6
| * | Extract connection checking logic from expand_module in hierarchy.ccRupert Swarbrick2021-07-201-23/+64
| * | Extract missing module support in hierarchy.cc to a helper functionRupert Swarbrick2021-07-141-44/+68
| * | Delete unused found_init variableRupert Swarbrick2021-07-141-3/+0
| * | rtlil: Make Process handling more uniform with Cell and Wire.Marcelina Kościelnicka2021-07-123-16/+12
| * | Move interface expansion in hierarchy.cc into a helper classRupert Swarbrick2021-06-161-100/+189
| * | opt_muxtree: Update port_off and port_idx even for constant bitsgatecat2021-06-111-17/+16
| * | opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.Marcelina Kościelnicka2021-06-091-122/+85
| * | opt_expr: Optimize div/mod by const 1.Marcelina Kościelnicka2021-06-091-4/+4
| * | Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-09149-154/+154
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| | * | Fix deadname SVN linksClaire Xenia Wolf2021-06-092-3/+3
| | * | Use HTTPS for website links, gatecat emailClaire Xenia Wolf2021-06-091-1/+1
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