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* | updated to use get_src_attribute() and set_src_attribute().Jason Lowdermilk2017-08-313-10/+7
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* | Add support for source line tracking through synthesis phaseJason Lowdermilk2017-08-293-4/+23
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* Rename recover_reduce to extract_reduce, fix args handlingClifford Wolf2017-08-282-8/+25
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* Merge branch 'recover-reduce' of https://github.com/azonenberg/yosys into ↵Clifford Wolf2017-08-282-0/+223
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| * recover_reduce: Update documentationRobert Ou2017-08-271-8/+11
| | | | | | | | | | The documentation now describes the commands performed in the deleted recover_reduce script.
| * recover_reduce: Reindent using tabsRobert Ou2017-08-271-190/+190
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| * recover_reduce: Rename recover_reduce_core to recover_reduceRobert Ou2017-08-273-101/+0
| | | | | | | | | | | | | | | | Clifford has commented on PR #387 stating that he does not like the driver script and would prefer to only have the core script with appropriate notes in the documentation. Also rename to .cc (rather than .cpp) for consistency.
| * recover_reduce: Add driver script for the $reduce_* recover featureRobert Ou2017-08-272-0/+101
| | | | | | | | | | Conflicts: passes/techmap/Makefile.inc
| * recover_reduce_core: Finish implementing the core functionRobert Ou2017-08-271-0/+110
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| * recover_reduce_core: Initial commitRobert Ou2017-08-272-0/+110
| | | | | | | | | | Conflicts: passes/techmap/Makefile.inc
* | Further improve extract_fa passClifford Wolf2017-08-281-1/+42
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* Don't track , ... contradictions through x/z-bitsClifford Wolf2017-08-251-1/+4
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* Add removing of redundant pairs of bits in ==, ===, !=, and !== to opt_exprClifford Wolf2017-08-251-0/+72
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* Further improve extract_fa (seems to be fully functional now)Clifford Wolf2017-08-251-10/+226
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* Rename "adders" to "extract_fa"Clifford Wolf2017-08-252-28/+16
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* Towards more generic "adder" function extractorClifford Wolf2017-08-231-202/+53
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* Add experimental adders passClifford Wolf2017-08-222-0/+447
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* Remove some dead code from fsm_mapClifford Wolf2017-08-211-3/+0
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* Rename "singleton" pass to "uniquify"Clifford Wolf2017-08-203-21/+22
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* More intuitive handling of "cd .." for singleton modulesClifford Wolf2017-08-191-2/+38
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* Add "sim -zinit -rstlen"Clifford Wolf2017-08-181-1/+53
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* Add "sim" support for memoriesClifford Wolf2017-08-181-2/+136
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* Add support for assert/assume/cover to "sim" commandClifford Wolf2017-08-181-4/+47
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* Add writeback mode to "sim" commandClifford Wolf2017-08-171-0/+44
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* Improve "sim" commandClifford Wolf2017-08-171-54/+272
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* Add "sim" command skeletonClifford Wolf2017-08-162-0/+372
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* Mostly coding style related fixes in rmports passClifford Wolf2017-08-151-30/+33
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* Merge branch 'rmports' of https://github.com/azonenberg/yosys into ↵Clifford Wolf2017-08-152-0/+185
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| * rmports: Now remove ports from cell instances if we optimized them out of ↵Andrew Zonenberg2017-08-141-2/+35
| | | | | | | | that cell
| * ProcessModule is no longer virtual (why was it in the first place?)Andrew Zonenberg2017-08-141-1/+1
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| * rmports now works on all modules in the design, not just the top.Andrew Zonenberg2017-08-141-4/+7
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| * Updated Makefile to reflect opt_rmports being renamed to rmportsAndrew Zonenberg2017-08-141-1/+1
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| * Renamed opt_rmports pass to rmportsAndrew Zonenberg2017-08-141-5/+5
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| * Improved handling of constant connections in opt_rmportsAndrew Zonenberg2017-08-141-0/+2
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| * Fixed handling of cell ports that aren't wiresAndrew Zonenberg2017-08-141-0/+3
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| * opt_rmports: Fixed incorrect handling of multi-bit netsAndrew Zonenberg2017-08-141-12/+27
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| * Removed commented out debug codeAndrew Zonenberg2017-08-141-4/+0
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| * Added opt_rmports pass (remove unconnected ports from top-level modules)Andrew Zonenberg2017-08-142-0/+133
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* | abc: Allow +/ filenames in the abc commandRobert Ou2017-08-141-0/+3
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* Add support for set-reset cell variants to opt_rmdffClifford Wolf2017-08-091-0/+182
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* Add handling of constant reset signals to opt_rmdffClifford Wolf2017-08-061-1/+23
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* Fix typo in "abc" pass help messageClifford Wolf2017-07-291-1/+1
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* Add consolidation of init attributes to opt_clean, some opt_clean log fixesClifford Wolf2017-07-291-6/+82
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* Add "opt_expr -fine" feature to remove neutral bits from reduce and logic ↵Clifford Wolf2017-07-261-0/+47
| | | | operators
* Add error for cell output ports that are connected to constantsClifford Wolf2017-07-221-20/+21
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* Fix handling of empty cell port assignments (i.e. ignore them)Clifford Wolf2017-07-212-0/+6
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* Add $alu to list of supported cells for "stat -width"Clifford Wolf2017-07-141-1/+1
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* Excluded $_TBUF_ from opt_merge passSalvador E. Tropea2017-07-031-0/+1
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* Fix and_or_buffer optimization in opt_expr for signed operatorsClifford Wolf2017-07-011-2/+2
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* Add "design -import"Clifford Wolf2017-06-301-3/+94
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