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| author | Clifford Wolf <clifford@clifford.at> | 2017-07-01 16:05:26 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-07-01 16:05:26 +0200 |
| commit | 0a02cdb93bfff64eb434e4cabbc9f007c4755647 (patch) | |
| tree | 6d8ca2a009fcea2013c7f56e6ade1dd50934f298 /passes | |
| parent | 7d2fb6e2fc8e2cdd9eebe40cd04256be8f590012 (diff) | |
| download | yosys-0a02cdb93bfff64eb434e4cabbc9f007c4755647.tar.gz yosys-0a02cdb93bfff64eb434e4cabbc9f007c4755647.tar.bz2 yosys-0a02cdb93bfff64eb434e4cabbc9f007c4755647.zip | |
Fix and_or_buffer optimization in opt_expr for signed operators
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_expr.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 07cdf4652..f9e40869d 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -371,13 +371,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (cell->type.in("$reduce_and", "$_AND_")) detect_const_and = true; - if (cell->type.in("$and", "$logic_and") && GetSize(cell->getPort("\\A")) == 1 && GetSize(cell->getPort("\\B")) == 1) + if (cell->type.in("$and", "$logic_and") && GetSize(cell->getPort("\\A")) == 1 && GetSize(cell->getPort("\\B")) == 1 && !cell->getParam("\\A_SIGNED").as_bool()) detect_const_and = true; if (cell->type.in("$reduce_or", "$reduce_bool", "$_OR_")) detect_const_or = true; - if (cell->type.in("$or", "$logic_or") && GetSize(cell->getPort("\\A")) == 1 && GetSize(cell->getPort("\\B")) == 1) + if (cell->type.in("$or", "$logic_or") && GetSize(cell->getPort("\\A")) == 1 && GetSize(cell->getPort("\\B")) == 1 && !cell->getParam("\\A_SIGNED").as_bool()) detect_const_or = true; if (detect_const_and || detect_const_or) |