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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-11 16:16:25 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-14 10:28:16 -0700 |
| commit | 2877d5e50449dd08ebcb183218d015008c9fffcb (patch) | |
| tree | df4a19e09599aa03761bfb49214a1a2178cb0565 /passes | |
| parent | 3dd7f42e2b07c84178c648a0c3979c61fe25f68f (diff) | |
| download | yosys-2877d5e50449dd08ebcb183218d015008c9fffcb.tar.gz yosys-2877d5e50449dd08ebcb183218d015008c9fffcb.tar.bz2 yosys-2877d5e50449dd08ebcb183218d015008c9fffcb.zip | |
Fixed handling of cell ports that aren't wires
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_rmports.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/opt/opt_rmports.cc b/passes/opt/opt_rmports.cc index afbbecf84..5522dfa8e 100644 --- a/passes/opt/opt_rmports.cc +++ b/passes/opt/opt_rmports.cc @@ -90,6 +90,9 @@ struct OptRmportsPass : public Pass { for(int i=0; i<conn.second.size(); i++) { auto sig = conn.second[i].wire; + if(sig == NULL) + continue; + //log(" sig %s\n", sig->name.c_str()); if( (sig->port_input || sig->port_output) && (used_ports.find(sig->name) == used_ports.end()) ) used_ports.emplace(sig->name); |