| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Remove &verify -s | Eddie Hung | 2019-12-17 | 1 | -1/+1 |
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| * | Use pool<> instead of std::set<> to preserver ordering | Eddie Hung | 2019-12-17 | 1 | -6/+6 |
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| * | Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop | Eddie Hung | 2019-12-16 | 1 | -5/+27 |
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| * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-12 | 1 | -8/+67 |
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| | * | Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr | Eddie Hung | 2019-12-09 | 1 | -8/+67 |
| | |\ | | | | | | | Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER | ||||
| | | * | ice40_wrapcarry -unwrap to preserve 'src' attribute | Eddie Hung | 2019-12-09 | 1 | -1/+9 |
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| | | * | -unwrap to create $lut not SB_LUT4 for opt_lut | Eddie Hung | 2019-12-09 | 1 | -7/+5 |
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| | | * | Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4 | Eddie Hung | 2019-12-09 | 1 | -7/+11 |
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| | | * | ice40_wrapcarry to really preserve attributes via -unwrap option | Eddie Hung | 2019-12-09 | 1 | -17/+55 |
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| | | * | Drop keep=0 attributes on SB_CARRY | Eddie Hung | 2019-12-06 | 1 | -0/+8 |
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| | | * | Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-12-05 | 1 | -0/+1 |
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| | | * | ice40_wrapcarry to preserve SB_CARRY's attributes | Eddie Hung | 2019-12-03 | 1 | -0/+2 |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-06 | 2 | -175/+137 |
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| | * | | iopadmap: Refactor and fix tristate buffer mapping. (#1527) | Marcin Kościelnicki | 2019-12-04 | 1 | -146/+97 |
| | |/ | | | | | | | | | | | | | The previous code for rerouting wires when inserting tristate buffers was overcomplicated and didn't handle all cases correctly (in particular, only cell connections were rewired — internal connections were not). | ||||
| | * | abc9: Fix breaking of SCCs | David Shah | 2019-12-01 | 1 | -29/+40 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | Call abc9 with "&write -n", and parse_xaiger() to cope | Eddie Hung | 2019-12-06 | 1 | -2/+2 |
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| * | | Fix abc9 re-integration, remove abc9_control_wire, use cell->type as | Eddie Hung | 2019-12-06 | 1 | -39/+15 |
| | | | | | | | | | as part of clock domain for mergeability class | ||||
| * | | abc9 to do clock partitioning again | Eddie Hung | 2019-12-05 | 1 | -37/+144 |
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| * | | Remove clkpart | Eddie Hung | 2019-12-05 | 2 | -309/+0 |
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| * | | Add assertion | Eddie Hung | 2019-12-03 | 1 | -0/+1 |
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| * | | Add abc9_init wire, attach to abc9_flop cell | Eddie Hung | 2019-12-03 | 1 | -2/+12 |
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| * | | Cleanup | Eddie Hung | 2019-12-01 | 1 | -3/+2 |
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| * | | Use pool instead of std::set for determinism | Eddie Hung | 2019-12-01 | 1 | -1/+1 |
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| * | | Use pool<> not std::set<> for determinism | Eddie Hung | 2019-12-01 | 1 | -4/+4 |
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| * | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-28 | 1 | -1/+1 |
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| | * | | Move \init signal for non-port signals as long as internally driven | Eddie Hung | 2019-11-28 | 1 | -1/+1 |
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| | * | | Fix multiple driver issue | Eddie Hung | 2019-11-27 | 1 | -2/+7 |
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| * | | | Fix multiple driver issue | Eddie Hung | 2019-11-27 | 1 | -2/+7 |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-27 | 3 | -7/+18 |
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| | * | | Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd | Eddie Hung | 2019-11-27 | 1 | -3/+3 |
| | |\ \ | | | | | | | | | xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder | ||||
| | | * | | Check for either sign or zero extension for postAdd packing | Eddie Hung | 2019-11-26 | 1 | -3/+3 |
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| | * | | | Merge pull request #1501 from YosysHQ/dave/mem_copy_attr | Clifford Wolf | 2019-11-27 | 1 | -0/+4 |
| | |\ \ \ | | | | | | | | | | | memory_collect: Copy attr from RTLIL::Memory to cell | ||||
| | | * | | | memory_collect: Copy attr from RTLIL::Memory to cell | David Shah | 2019-11-18 | 1 | -0/+4 |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | | | | opt_share: Fix handling of fine cells. | Marcin Kościelnicki | 2019-11-27 | 1 | -4/+11 |
| | | |/ / | |/| | | | | | | | | | | Fixes #1525. | ||||
| * | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -7/+3 |
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| | * | | | Do not replace constants with same wire | Eddie Hung | 2019-11-27 | 1 | -7/+3 |
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| * | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -47/+71 |
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| | * | | | Cleanup | Eddie Hung | 2019-11-27 | 1 | -5/+3 |
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| | * | | | Check for nullptr | Eddie Hung | 2019-11-27 | 1 | -1/+1 |
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| | * | | | Stray log_dump | Eddie Hung | 2019-11-27 | 1 | -1/+0 |
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| | * | | | Revert "submod to bitty rather bussy, for bussy wires used as input and output" | Eddie Hung | 2019-11-27 | 1 | -40/+71 |
| | | | | | | | | | | | | | | | | | This reverts commit cba3073026711e7683c46ba091c56a5c5a041a45. | ||||
| | * | | | Promote output wires in sigmap so that can be detected | Eddie Hung | 2019-11-26 | 1 | -8/+4 |
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| | * | | | Fix submod -hidden | Eddie Hung | 2019-11-26 | 1 | -5/+6 |
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| | * | | | Add -hidden option to submod | Eddie Hung | 2019-11-26 | 1 | -11/+25 |
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| | * | | | Update docs with bullet points | Eddie Hung | 2019-11-26 | 1 | -10/+9 |
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| | * | | | Move \init from source wire to submod if output port | Eddie Hung | 2019-11-25 | 1 | -0/+7 |
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| * | | | | Fix submod -hidden | Eddie Hung | 2019-11-26 | 1 | -5/+6 |
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| * | | | | clkpart to use 'submod -hidden' | Eddie Hung | 2019-11-26 | 1 | -1/+1 |
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| * | | | | Add -hidden option to submod | Eddie Hung | 2019-11-26 | 1 | -20/+40 |
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| * | | | | Fix debug | Eddie Hung | 2019-11-25 | 1 | -3/+3 |
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index : iCE40/yosys | |
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