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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-01 23:26:17 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-01 23:26:17 -0800 |
| commit | 1d87488795e4f898e2fcf6a71259a3972dbe7819 (patch) | |
| tree | 63a93be231525c301e21039071d7d64d70d623c6 /passes | |
| parent | 4ac1b92df33d1ef4bbed71216e2b39c4a0651e5b (diff) | |
| download | yosys-1d87488795e4f898e2fcf6a71259a3972dbe7819.tar.gz yosys-1d87488795e4f898e2fcf6a71259a3972dbe7819.tar.bz2 yosys-1d87488795e4f898e2fcf6a71259a3972dbe7819.zip | |
Use pool instead of std::set for determinism
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/hierarchy/submod.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 211f96175..3b4f33a60 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -42,7 +42,7 @@ struct SubmodWorker struct SubModule { std::string name, full_name; - std::set<RTLIL::Cell*> cells; + pool<RTLIL::Cell*> cells; }; std::map<std::string, SubModule> submodules; |