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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 13:21:59 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 13:23:31 -0800 |
| commit | 130d3b9639148fa8191937313a3ad21a7827df18 (patch) | |
| tree | 1ccf5d579584ed9a11c9ea40c560c0bc09f07cc9 /passes | |
| parent | ff1e35768224a7824ec9838ca84d27bbb4a14676 (diff) | |
| download | yosys-130d3b9639148fa8191937313a3ad21a7827df18.tar.gz yosys-130d3b9639148fa8191937313a3ad21a7827df18.tar.bz2 yosys-130d3b9639148fa8191937313a3ad21a7827df18.zip | |
Fix multiple driver issue
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/hierarchy/submod.cc | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index b21b0de01..839f8561c 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -228,11 +228,16 @@ struct SubmodWorker RTLIL::SigSpec old_sig = sigmap(it.first); RTLIL::Wire *new_wire = it.second.new_wire; if (new_wire->port_id > 0) { - // Prevents "ERROR: Mismatch in directionality ..." when flattening if (new_wire->port_output) - for (auto &b : old_sig) + for (int i = 0; i < GetSize(old_sig); i++) { + auto &b = old_sig[i]; + // Prevents "ERROR: Mismatch in directionality ..." when flattening if (!b.wire) b = module->addWire(NEW_ID); + // Prevents "Warning: multiple conflicting drivers ..." + else if (!it.second.is_int_driven[i]) + b = module->addWire(NEW_ID); + } new_cell->setPort(new_wire->name, old_sig); } } |