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* Added $ff and $_FF_ cell typesClifford Wolf2016-10-122-8/+50
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* Added "opt_rmdff -keepdc"Clifford Wolf2016-09-302-7/+20
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* Cosmetic fix in test_autotb.ccClifford Wolf2016-09-191-2/+2
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* Avoid creating very long strings in test_autotbClifford Wolf2016-09-191-4/+10
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* Bugfix in techmap parameter handlingClifford Wolf2016-09-141-1/+1
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* Typo fix.Kaj Tuomi2016-09-081-1/+1
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* Improvements in assertpmuxClifford Wolf2016-09-071-21/+158
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* Added assertpmuxClifford Wolf2016-09-072-0/+104
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* Added "tee +INT -INT"Clifford Wolf2016-09-061-0/+10
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* Run log_flush() before solving in sat commandClifford Wolf2016-09-061-0/+3
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* Improved init spec handling in opt_rmdff, modernized the code a bitClifford Wolf2016-08-301-39/+82
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* Removed $predict againClifford Wolf2016-08-283-3/+2
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* Improved "show" help messageClifford Wolf2016-08-281-3/+5
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* Fixed handling of transparent bram rd ports on ROMsClifford Wolf2016-08-271-0/+3
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* Fixed bug in memory_share for memory ports with different ABITSClifford Wolf2016-08-221-0/+6
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* Added "wreduce -memx"Clifford Wolf2016-08-201-3/+14
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* Added memory_memx pass, "memory -memx", and "prep -memx"Clifford Wolf2016-08-193-2/+104
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* Optimize memory address port width in wreduce and memory_collect, not ↵Clifford Wolf2016-08-192-3/+31
| | | | verilog front-end
* Bugfix in test_autotbClifford Wolf2016-08-181-0/+4
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* Fixed use-after-free dict<> usage pattern in hierarchy.ccClifford Wolf2016-08-161-1/+3
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* Minor fixes in show commandClifford Wolf2016-08-161-3/+3
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* Fixed some compiler warnings in attrmap commandClifford Wolf2016-08-101-4/+4
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* Added "attrmap" commandClifford Wolf2016-08-093-0/+253
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* Added "attrmvcp" passClifford Wolf2016-08-092-0/+138
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* Undo "preserve wire attributes in iopadmap" change (it was OK before)Clifford Wolf2016-08-081-1/+1
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* Added "test_autotb -seed" (and "autotest.sh -S")Clifford Wolf2016-08-061-3/+8
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* preserve wire attributes in iopadmapClifford Wolf2016-08-061-1/+1
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* Added "insbuf" commandClifford Wolf2016-08-022-0/+95
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* Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()Clifford Wolf2016-07-251-1/+1
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* Improvements in CellEdgesDatabaseClifford Wolf2016-07-241-3/+33
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* Added CellEdgesDatabase APIClifford Wolf2016-07-241-0/+96
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* Moved SatHelper::setup_init() code to SatHelper::setup()Clifford Wolf2016-07-241-97/+92
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* Added $initstate support to "sat" commandClifford Wolf2016-07-231-13/+12
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* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-213-3/+3
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* Added basic support for $expect cellsClifford Wolf2016-07-133-2/+4
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* Minor bugfix in FSM reset state detectionClifford Wolf2016-07-121-2/+5
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* Further improved fsm_detect output, attempt to detect self-resetting circuitsClifford Wolf2016-07-091-6/+68
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* Added printing of some warning messages to fsm_detectClifford Wolf2016-07-091-14/+61
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* Replaced "select -assert-limit" with -assert-max and -assert-minClifford Wolf2016-07-011-42/+29
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* Added 'assert-limit' option for 'select' commandeshellko2016-07-011-5/+42
| | | For resource limited designs such as FPGA it can be useful to specify limit of specific resources available on board. So user can check if he should change RTL as early as mapping done.
* Bugfix in "abc -script" handlingClifford Wolf2016-06-191-53/+50
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* Added "deminout"Clifford Wolf2016-06-192-0/+117
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* Added "dc2" to default ABC scriptsClifford Wolf2016-06-171-5/+5
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* Added "abc -I <num> -P <num>"Clifford Wolf2016-06-171-8/+33
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* Improved support for $sop cellsClifford Wolf2016-06-172-2/+69
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* Added $sop cell type and "abc -sop"Clifford Wolf2016-06-171-6/+23
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* Updated ABC to hg rev b5df6e2b76f0Clifford Wolf2016-06-171-9/+9
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* Added "nlutmap -assert"Clifford Wolf2016-06-091-0/+14
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* Added "proc_mux -ifx"Clifford Wolf2016-06-062-19/+43
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* Added "setundef -init"Clifford Wolf2016-06-031-5/+89
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