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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-25 16:39:25 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-25 16:39:25 +0200 |
| commit | 8537c4d2061db1ee11defc357781c6c534be5b3d (patch) | |
| tree | 4fe2f7e4f7082ee6add823da39910912a52dc6e1 /passes | |
| parent | 5b944ef11b8964a00d833ad29c96ad46da06f7a3 (diff) | |
| download | yosys-8537c4d2061db1ee11defc357781c6c534be5b3d.tar.gz yosys-8537c4d2061db1ee11defc357781c6c534be5b3d.tar.bz2 yosys-8537c4d2061db1ee11defc357781c6c534be5b3d.zip | |
Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/tests/test_cell.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 8e9dc3112..19fad01ef 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -344,7 +344,7 @@ static void run_edges_test(RTLIL::Design *design, bool verbose) SatGen satgen(&ez, &sigmap); FwdCellEdgesDatabase edges_db(sigmap); - if (!edges_db.add_cell(cell)) + if (!edges_db.add_edges_from_cell(cell)) log_error("Creating edge database failed for this cell!\n"); dict<SigBit, pool<SigBit>> satgen_db; |