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author | Clifford Wolf <clifford@clifford.at> | 2016-06-09 11:47:41 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2016-06-09 11:47:41 +0200 |
commit | 99edf249669158b8c8bef0c7c3b926a2bbb7a621 (patch) | |
tree | 8f149c3141c37228846f583fdde7080f115d8d26 /passes | |
parent | 52b0b4e31e98816bc15b957c89bca76619231143 (diff) | |
download | yosys-99edf249669158b8c8bef0c7c3b926a2bbb7a621.tar.gz yosys-99edf249669158b8c8bef0c7c3b926a2bbb7a621.tar.bz2 yosys-99edf249669158b8c8bef0c7c3b926a2bbb7a621.zip |
Added "nlutmap -assert"
Diffstat (limited to 'passes')
-rw-r--r-- | passes/techmap/nlutmap.cc | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/passes/techmap/nlutmap.cc b/passes/techmap/nlutmap.cc index a6d4e1a2f..6fcdf82bd 100644 --- a/passes/techmap/nlutmap.cc +++ b/passes/techmap/nlutmap.cc @@ -26,6 +26,7 @@ PRIVATE_NAMESPACE_BEGIN struct NlutmapConfig { vector<int> luts; + bool assert_mode = false; }; struct NlutmapWorker @@ -116,6 +117,12 @@ struct NlutmapWorker available_luts.back() += n_luts; } + if (config.assert_mode) { + for (auto cell : module->cells()) + if (cell->type == "$lut" && !mapped_cells.count(cell)) + log_error("Insufficient number of LUTs to map all logic cells!\n"); + } + run_abc(0); } }; @@ -135,6 +142,9 @@ struct NlutmapPass : public Pass { log(" The number of LUTs with 1, 2, 3, ... inputs that are\n"); log(" available in the target architecture.\n"); log("\n"); + log(" -assert\n"); + log(" Create an error if not all logic can be mapped\n"); + log("\n"); log("Excess logic that does not fit into the specified LUTs is mapped back\n"); log("to generic logic gates ($_AND_, etc.).\n"); log("\n"); @@ -156,6 +166,10 @@ struct NlutmapPass : public Pass { config.luts.push_back(atoi(token.c_str())); continue; } + if (args[argidx] == "-assert") { + config.assert_mode = true; + continue; + } break; } extra_args(args, argidx, design); |