| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | * | | Initial adaptation of muxpack from shregmap | Eddie Hung | 2019-06-06 | 1 | -0/+1 | |
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| | * | Merge pull request #1071 from YosysHQ/eddie/fix_1070 | Clifford Wolf | 2019-06-06 | 1 | -2/+2 | |
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| | | * | Fix typo in opt_rmdff | Eddie Hung | 2019-06-05 | 1 | -2/+2 | |
| | * | | Merge pull request #1072 from YosysHQ/eddie/fix_1069 | Clifford Wolf | 2019-06-06 | 1 | -0/+5 | |
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| | | * | | Error out if no top module given before 'sim' | Eddie Hung | 2019-06-05 | 1 | -0/+5 | |
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| | * / | Missing doc for -tech xilinx in shregmap | Eddie Hung | 2019-06-05 | 1 | -0/+3 | |
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| | * | Merge pull request #1067 from YosysHQ/clifford/fix1065 | Eddie Hung | 2019-06-05 | 1 | -1/+1 | |
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| * | | | shregmap -tech xilinx_static to handle INIT | Eddie Hung | 2019-06-05 | 1 | -22/+32 | |
| * | | | Continue support for ShregmapTechXilinx7Static | Eddie Hung | 2019-06-05 | 1 | -30/+81 | |
| * | | | Add -tech xilinx_static | Eddie Hung | 2019-06-05 | 1 | -2/+13 | |
| * | | | Refactor to ShregmapTechXilinx7Static | Eddie Hung | 2019-06-05 | 1 | -46/+86 | |
| * | | | shregmap -tech xilinx_dynamic to work -params and -enpol | Eddie Hung | 2019-06-05 | 1 | -6/+26 | |
| * | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-06-05 | 2 | -27/+95 | |
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| | * | | Major rewrite of wire selection in setundef -init | Clifford Wolf | 2019-06-05 | 1 | -30/+89 | |
| | * | | Indent fix | Clifford Wolf | 2019-06-05 | 1 | -23/+25 | |
| | * | | Merge pull request #999 from jakobwenzel/setundefInitFix | Clifford Wolf | 2019-06-05 | 1 | -16/+23 | |
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| | | * | | initialize more registers in setundef -init | Jakob Wenzel | 2019-05-09 | 1 | -16/+23 | |
| | * | | | Fix typo in fmcombine log message, fixes #1063 | Clifford Wolf | 2019-06-05 | 1 | -2/+2 | |
| * | | | | Merge remote-tracking branch 'origin/clifford/fix1065' into xc7mux | Eddie Hung | 2019-06-05 | 1 | -1/+1 | |
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| | * | | | Suppress driver-driver conflict warning for unknown cell types, fixes #1065 | Clifford Wolf | 2019-06-05 | 1 | -1/+1 | |
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| * | | | Rename shregmap -tech xilinx -> xilinx_dynamic | Eddie Hung | 2019-06-04 | 1 | -4/+4 | |
| * | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-06-03 | 2 | -4/+16 | |
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| | * | | Fix "tee" handling of log_streams | Clifford Wolf | 2019-05-31 | 1 | -0/+5 | |
| | * | | Merge pull request #1049 from YosysHQ/clifford/fix1047 | Clifford Wolf | 2019-05-28 | 1 | -4/+11 | |
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| | | * | | Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047 | Clifford Wolf | 2019-05-28 | 1 | -4/+11 | |
| * | | | | Remove dupe | Eddie Hung | 2019-06-03 | 1 | -7/+7 | |
| * | | | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-05-31 | 1 | -6/+0 | |
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| | * | | | | Move clean from aigerparse to abc9 | Eddie Hung | 2019-04-23 | 1 | -0/+1 | |
| | * | | | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-04-22 | 1 | -5/+159 | |
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| | | * \ \ \ | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-22 | 1 | -5/+159 | |
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| | * | | | | | | Tidy up | Eddie Hung | 2019-04-22 | 1 | -6/+0 | |
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| * | | | | | | Throw out unused code inherited from abc | Eddie Hung | 2019-05-31 | 1 | -212/+3 | |
| * | | | | | | Fix spelling | Eddie Hung | 2019-05-30 | 1 | -1/+1 | |
| * | | | | | | Revert "Re-enable &dc2" | Eddie Hung | 2019-05-30 | 1 | -1/+1 | |
| * | | | | | | Do not double count LUT1s | Eddie Hung | 2019-05-30 | 1 | -1/+0 | |
| * | | | | | | Re-enable &dc2 | Eddie Hung | 2019-05-30 | 1 | -1/+1 | |
| * | | | | | | Reduce -W to 160 | Eddie Hung | 2019-05-29 | 1 | -1/+1 | |
| * | | | | | | Erase all boxes before stitching | Eddie Hung | 2019-05-29 | 1 | -27/+30 | |
| * | | | | | | Call &if with -W 250 | Eddie Hung | 2019-05-29 | 1 | -1/+6 | |
| * | | | | | | Add some debug to abc9 | Eddie Hung | 2019-05-29 | 1 | -1/+19 | |
| * | | | | | | From master | Eddie Hung | 2019-05-28 | 1 | -1/+1 | |
| * | | | | | | Update from master | Eddie Hung | 2019-05-28 | 2 | -3/+1 | |
| * | | | | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-28 | 3 | -50/+203 | |
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| | * | | | | | Refactor hierarchy wand/wor handling | Clifford Wolf | 2019-05-28 | 1 | -102/+143 | |
| | * | | | | | Merge branch 'master' into wandwor | Stefan Biereigel | 2019-05-27 | 2 | -6/+71 | |
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| | | * | | | | Merge pull request #1026 from YosysHQ/clifford/fix1023 | Clifford Wolf | 2019-05-27 | 1 | -2/+3 | |
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| | | | * | | | | Keep zero-width wires in opt_clean if and only if they are ports, fixes #1023 | Clifford Wolf | 2019-05-22 | 1 | -2/+3 | |
| | | * | | | | | Revert enable check | Eddie Hung | 2019-05-25 | 1 | -3/+1 | |
| | | * | | | | | opt_rmdff to optimise even in presence of enable signal, even removing | Eddie Hung | 2019-05-24 | 1 | -12/+29 | |
| | | * | | | | | Add comments | Eddie Hung | 2019-05-24 | 1 | -1/+22 | |
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index : iCE40/yosys | |
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