Merge remote-tracking branch 'origin/master' into xc7mux

3 files changed, 203 insertions, 50 deletions

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 72bc2e133..24e64a9b2 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -562,7 +562,8 @@ struct HierarchyPass : public Pass {
 		log("In parametric designs, a module might exists in several variations with\n");
 		log("different parameter values. This pass looks at all modules in the current\n");
 		log("design an re-runs the language frontends for the parametric modules as\n");
-		log("needed.\n");
+		log("needed. It also resolves assignments to wired logic data types (wand/wor),\n");
+		log("resolves positional module parameters, unroll array instances, and more.\n");
 		log("\n");
 		log("    -check\n");
 		log("        also check the design hierarchy. this generates an error when\n");
@@ -943,62 +944,178 @@ struct HierarchyPass : public Pass {
 		std::vector<Module*> design_modules = design->modules();
 
 		for (auto module : design_modules)
-		for (auto cell : module->cells())
 		{
-			Module *m = design->module(cell->type);
+			pool<Wire*> wand_wor_index;
+			dict<Wire*, SigSpec> wand_map, wor_map;
+			vector<SigSig> new_connections;
 
-			if (m == nullptr)
-				continue;
+			for (auto wire : module->wires())
+			{
+				if (wire->get_bool_attribute("\\wand")) {
+					wand_map[wire] = SigSpec();
+					wand_wor_index.insert(wire);
+				}
+				if (wire->get_bool_attribute("\\wor")) {
+					wor_map[wire] = SigSpec();
+					wand_wor_index.insert(wire);
+				}
+			}
+
+			for (auto &conn : module->connections())
+			{
+				SigSig new_conn;
+				int cursor = 0;
+
+				for (auto c : conn.first.chunks())
+				{
+					Wire *w = c.wire;
+					SigSpec rhs = conn.second.extract(cursor, GetSize(c));
+
+					if (wand_wor_index.count(w) == 0) {
+						new_conn.first.append(c);
+						new_conn.second.append(rhs);
+					} else {
+						if (wand_map.count(w)) {
+							SigSpec sig = SigSpec(State::S1, GetSize(w));
+							sig.replace(c.offset, rhs);
+							wand_map.at(w).append(sig);
+						} else {
+							SigSpec sig = SigSpec(State::S0, GetSize(w));
+							sig.replace(c.offset, rhs);
+							wor_map.at(w).append(sig);
+						}
+					}
+					cursor += GetSize(c);
+				}
+				new_connections.push_back(new_conn);
+			}
+			module->new_connections(new_connections);
 
-			if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) {
-				IdString new_m_name = m->derive(design, cell->parameters, true);
-				if (new_m_name.empty())
+			for (auto cell : module->cells())
+			{
+				if (!cell->known())
 					continue;
-				if (new_m_name != m->name) {
-					m = design->module(new_m_name);
-					blackbox_derivatives.insert(m);
+
+				for (auto &conn : cell->connections())
+				{
+					if (!cell->output(conn.first))
+						continue;
+
+					SigSpec new_sig;
+					bool update_port = false;
+
+					for (auto c : conn.second.chunks())
+					{
+						Wire *w = c.wire;
+
+						if (wand_wor_index.count(w) == 0) {
+							new_sig.append(c);
+							continue;
+						}
+
+						Wire *t = module->addWire(NEW_ID, GetSize(c));
+						new_sig.append(t);
+						update_port = true;
+
+						if (wand_map.count(w)) {
+							SigSpec sig = SigSpec(State::S1, GetSize(w));
+							sig.replace(c.offset, t);
+							wand_map.at(w).append(sig);
+						} else {
+							SigSpec sig = SigSpec(State::S0, GetSize(w));
+							sig.replace(c.offset, t);
+							wor_map.at(w).append(sig);
+						}
+					}
+
+					if (update_port)
+						cell->setPort(conn.first, new_sig);
 				}
 			}
 
-			for (auto &conn : cell->connections())
+			for (auto w : wand_wor_index)
 			{
-				Wire *w = m->wire(conn.first);
+				bool wand = wand_map.count(w);
+				SigSpec sigs = wand ? wand_map.at(w) : wor_map.at(w);
 
-				if (w == nullptr || w->port_id == 0)
+				if (GetSize(sigs) == 0)
 					continue;
 
-				if (GetSize(conn.second) == 0)
+				if (GetSize(w) == 1) {
+					if (wand)
+						module->addReduceAnd(NEW_ID, sigs, w);
+					else
+						module->addReduceOr(NEW_ID, sigs, w);
 					continue;
+				}
 
-				SigSpec sig = conn.second;
+				SigSpec s = sigs.extract(0, GetSize(w));
+				for (int i = GetSize(w); i < GetSize(sigs); i += GetSize(w)) {
+					if (wand)
+						s = module->And(NEW_ID, s, sigs.extract(i, GetSize(w)));
+					else
+						s = module->Or(NEW_ID, s, sigs.extract(i, GetSize(w)));
+				}
+				module->connect(w, s);
+			}
 
-				if (!keep_portwidths && GetSize(w) != GetSize(conn.second))
-				{
-					if (GetSize(w) < GetSize(conn.second))
-					{
-						int n = GetSize(conn.second) - GetSize(w);
-						if (!w->port_input && w->port_output)
-							module->connect(sig.extract(GetSize(w), n), Const(0, n));
-						sig.remove(GetSize(w), n);
+			for (auto cell : module->cells())
+			{
+				Module *m = design->module(cell->type);
+
+				if (m == nullptr)
+					continue;
+
+				if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) {
+					IdString new_m_name = m->derive(design, cell->parameters, true);
+					if (new_m_name.empty())
+						continue;
+					if (new_m_name != m->name) {
+						m = design->module(new_m_name);
+						blackbox_derivatives.insert(m);
 					}
-					else
+				}
+
+				for (auto &conn : cell->connections())
+				{
+					Wire *w = m->wire(conn.first);
+
+					if (w == nullptr || w->port_id == 0)
+						continue;
+
+					if (GetSize(conn.second) == 0)
+						continue;
+
+					SigSpec sig = conn.second;
+
+					if (!keep_portwidths && GetSize(w) != GetSize(conn.second))
 					{
-						int n = GetSize(w) - GetSize(conn.second);
-						if (w->port_input && !w->port_output)
-							sig.append(Const(0, n));
+						if (GetSize(w) < GetSize(conn.second))
+						{
+							int n = GetSize(conn.second) - GetSize(w);
+							if (!w->port_input && w->port_output)
+								module->connect(sig.extract(GetSize(w), n), Const(0, n));
+							sig.remove(GetSize(w), n);
+						}
 						else
-							sig.append(module->addWire(NEW_ID, n));
+						{
+							int n = GetSize(w) - GetSize(conn.second);
+							if (w->port_input && !w->port_output)
+								sig.append(Const(0, n));
+							else
+								sig.append(module->addWire(NEW_ID, n));
+						}
+
+						if (!conn.second.is_fully_const() || !w->port_input || w->port_output)
+							log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", log_id(module), log_id(cell),
+									log_id(conn.first), GetSize(conn.second), GetSize(sig));
+						cell->setPort(conn.first, sig);
 					}
 
-					if (!conn.second.is_fully_const() || !w->port_input || w->port_output)
-						log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", log_id(module), log_id(cell),
-								log_id(conn.first), GetSize(conn.second), GetSize(sig));
-					cell->setPort(conn.first, sig);
+					if (w->port_output && !w->port_input && sig.has_const())
+						log_error("Output port %s.%s.%s (%s) is connected to constants: %s\n",
+								log_id(module), log_id(cell), log_id(conn.first), log_id(cell->type), log_signal(sig));
 				}
-
-				if (w->port_output && !w->port_input && sig.has_const())
-					log_error("Output port %s.%s.%s (%s) is connected to constants: %s\n",
-							log_id(module), log_id(cell), log_id(conn.first), log_id(cell->type), log_signal(sig));
 			}
 		}
 
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index bf8020169..7011d4602 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -319,8 +319,9 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 			wire->attributes.erase("\\init");
 
 		if (GetSize(wire) == 0) {
-			// delete zero-width wires
-			goto delete_this_wire;
+			// delete zero-width wires, unless they are module ports
+			if (wire->port_id == 0)
+				goto delete_this_wire;
 		} else
 		if (wire->port_id != 0 || wire->get_bool_attribute("\\keep") || !initval.is_fully_undef()) {
 			// do not delete anything with "keep" or module ports or initialized wires
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index 3cb8e2b1e..2abffa2a9 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -338,16 +338,6 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		val_init.bits.push_back(bit.wire == NULL ? bit.data : RTLIL::State::Sx);
 	}
 
-	if (sig_e.size()) {
-		if (!sig_e.is_fully_const())
-			return false;
-		if (sig_e != val_ep) {
-			if (has_init)
-				mod->connect(sig_q, val_init);
-			goto delete_dff;
-		}
-	}
-
 	if (dff->type.in("$ff", "$dff") && mux_drivers.has(sig_d)) {
 		std::set<RTLIL::Cell*> muxes;
 		mux_drivers.find(sig_d, muxes);
@@ -365,39 +355,60 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		}
 	}
 
+	// If clock is driven by a constant and (i) no reset signal
+	//                                      (ii) Q has no initial value
+	//                                      (iii) initial value is same as reset value
 	if (!sig_c.empty() && sig_c.is_fully_const() && (!sig_r.size() || !has_init || val_init == val_rv)) {
 		if (val_rv.bits.size() == 0)
 			val_rv = val_init;
+		// Q is permanently reset value or initial value
 		mod->connect(sig_q, val_rv);
 		goto delete_dff;
 	}
 
+	// If D is fully undefined and reset signal present and (i) Q has no initial value
+	//                                                     (ii) initial value is same as reset value
 	if (sig_d.is_fully_undef() && sig_r.size() && (!has_init || val_init == val_rv)) {
+		// Q is permanently reset value
 		mod->connect(sig_q, val_rv);
 		goto delete_dff;
 	}
 
+	// If D is fully undefined and no reset signal and Q has an initial value
 	if (sig_d.is_fully_undef() && !sig_r.size() && has_init) {
+		// Q is permanently initial value
 		mod->connect(sig_q, val_init);
 		goto delete_dff;
 	}
 
+	// If D is fully constant and (i) no reset signal
+	//                            (ii) reset value is same as constant D
+	//                        and (a) has no initial value
+	//                            (b) initial value same as constant D
 	if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const())) {
+		// Q is permanently D
 		mod->connect(sig_q, sig_d);
 		goto delete_dff;
 	}
 
+	// If D input is same as Q output and (i) no reset signal
+	//                                    (ii) no initial signal
+	//                                    (iii) initial value is same as reset value
 	if (sig_d == sig_q && (sig_r.empty() || !has_init || val_init == val_rv)) {
+		// Q is permanently reset value or initial value
 		if (sig_r.size())
 			mod->connect(sig_q, val_rv);
-		if (has_init)
+		else if (has_init)
 			mod->connect(sig_q, val_init);
 		goto delete_dff;
 	}
 
+	// If reset signal is present, and is fully constant
 	if (!sig_r.empty() && sig_r.is_fully_const())
 	{
+		// If reset value is permanently active or if reset is undefined
 		if (sig_r == val_rp || sig_r.is_fully_undef()) {
+			// Q is permanently reset value
 			mod->connect(sig_q, val_rv);
 			goto delete_dff;
 		}
@@ -417,6 +428,30 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		dff->unsetPort("\\R");
 	}
 
+	// If enable signal is present, and is fully constant
+	if (!sig_e.empty() && sig_e.is_fully_const())
+	{
+		// If enable value is permanently inactive
+		if (sig_e != val_ep) {
+			// Q is permanently initial value
+			mod->connect(sig_q, val_init);
+			goto delete_dff;
+		}
+
+		log("Removing unused enable from %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod));
+
+		if (dff->type == "$dffe") {
+			dff->type = "$dff";
+			dff->unsetPort("\\EN");
+			dff->unsetParam("\\EN_POLARITY");
+			return true;
+		}
+
+		log_assert(dff->type.substr(0,7) == "$_DFFE_");
+		dff->type = stringf("$_DFF_%c_", + dff->type[7]);
+		dff->unsetPort("\\E");
+	}
+
 	return false;
 
 delete_dff: