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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 17:47:05 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 17:47:05 -0700 |
| commit | 5f30a8795d9a3b2c4ebaaa16ecf186e35e82a04b (patch) | |
| tree | ef3a46cf16cb01e05b16697899a2f591a508c625 /passes | |
| parent | 8f30019b68c68258979137a9d9fbbe68794781c5 (diff) | |
| download | yosys-5f30a8795d9a3b2c4ebaaa16ecf186e35e82a04b.tar.gz yosys-5f30a8795d9a3b2c4ebaaa16ecf186e35e82a04b.tar.bz2 yosys-5f30a8795d9a3b2c4ebaaa16ecf186e35e82a04b.zip | |
Tidy up
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 18f860e36..67d0981f4 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -561,11 +561,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri output_bits.insert({wire, i}); } else { - //if (w->name == "\\__dummy_o__") { - // log("Don't call ABC as there is nothing to map.\n"); - // goto cleanup; - //} - // Attempt another wideports_split here because there // exists the possibility that different bits of a port // could be an input and output, therefore parse_xiager() @@ -935,7 +930,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // log("Don't call ABC as there is nothing to map.\n"); //} -cleanup: if (cleanup) { log("Removing temp directory.\n"); |