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* | | shregmap -tech xilinx_static to handle INITEddie Hung2019-06-051-22/+32
* | | Continue support for ShregmapTechXilinx7StaticEddie Hung2019-06-051-30/+81
* | | Add -tech xilinx_staticEddie Hung2019-06-051-2/+13
* | | Refactor to ShregmapTechXilinx7StaticEddie Hung2019-06-051-46/+86
* | | shregmap -tech xilinx_dynamic to work -params and -enpolEddie Hung2019-06-051-6/+26
* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-052-27/+95
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| * | Major rewrite of wire selection in setundef -initClifford Wolf2019-06-051-30/+89
| * | Indent fixClifford Wolf2019-06-051-23/+25
| * | Merge pull request #999 from jakobwenzel/setundefInitFixClifford Wolf2019-06-051-16/+23
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| | * | initialize more registers in setundef -initJakob Wenzel2019-05-091-16/+23
| * | | Fix typo in fmcombine log message, fixes #1063Clifford Wolf2019-06-051-2/+2
* | | | Merge remote-tracking branch 'origin/clifford/fix1065' into xc7muxEddie Hung2019-06-051-1/+1
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| * | | Suppress driver-driver conflict warning for unknown cell types, fixes #1065Clifford Wolf2019-06-051-1/+1
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* | | Rename shregmap -tech xilinx -> xilinx_dynamicEddie Hung2019-06-041-4/+4
* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-032-4/+16
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| * | Fix "tee" handling of log_streamsClifford Wolf2019-05-311-0/+5
| * | Merge pull request #1049 from YosysHQ/clifford/fix1047Clifford Wolf2019-05-281-4/+11
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| | * | Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047Clifford Wolf2019-05-281-4/+11
* | | | Remove dupeEddie Hung2019-06-031-7/+7
* | | | Merge branch 'xaig' into xc7muxEddie Hung2019-05-311-6/+0
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| * | | | Move clean from aigerparse to abc9Eddie Hung2019-04-231-0/+1
| * | | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-04-221-5/+159
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| | * \ \ \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-221-5/+159
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| * | | | | | Tidy upEddie Hung2019-04-221-6/+0
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* | | | | | Throw out unused code inherited from abcEddie Hung2019-05-311-212/+3
* | | | | | Fix spellingEddie Hung2019-05-301-1/+1
* | | | | | Revert "Re-enable &dc2"Eddie Hung2019-05-301-1/+1
* | | | | | Do not double count LUT1sEddie Hung2019-05-301-1/+0
* | | | | | Re-enable &dc2Eddie Hung2019-05-301-1/+1
* | | | | | Reduce -W to 160Eddie Hung2019-05-291-1/+1
* | | | | | Erase all boxes before stitchingEddie Hung2019-05-291-27/+30
* | | | | | Call &if with -W 250Eddie Hung2019-05-291-1/+6
* | | | | | Add some debug to abc9Eddie Hung2019-05-291-1/+19
* | | | | | From masterEddie Hung2019-05-281-1/+1
* | | | | | Update from masterEddie Hung2019-05-282-3/+1
* | | | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-283-50/+203
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| * | | | | Refactor hierarchy wand/wor handlingClifford Wolf2019-05-281-102/+143
| * | | | | Merge branch 'master' into wandworStefan Biereigel2019-05-272-6/+71
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| | * | | | Merge pull request #1026 from YosysHQ/clifford/fix1023Clifford Wolf2019-05-271-2/+3
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| | | * | | | Keep zero-width wires in opt_clean if and only if they are ports, fixes #1023Clifford Wolf2019-05-221-2/+3
| | * | | | | Revert enable checkEddie Hung2019-05-251-3/+1
| | * | | | | opt_rmdff to optimise even in presence of enable signal, even removingEddie Hung2019-05-241-12/+29
| | * | | | | Add commentsEddie Hung2019-05-241-1/+22
| | * | | | | Resolve @cliffordwolf review, set even if !has_initEddie Hung2019-05-241-2/+1
| * | | | | | move wand/wor resolution into hierarchy passStefan Biereigel2019-05-271-1/+77
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* | | | | | MisspellEddie Hung2019-05-281-1/+1
* | | | | | If driver not found, use LUT2Eddie Hung2019-05-271-29/+27
* | | | | | Disconnect all ABC boxes tooEddie Hung2019-05-271-11/+9
* | | | | | Parse without wideportsEddie Hung2019-05-271-1/+1
* | | | | | Remove mapped_mod when doneEddie Hung2019-05-271-0/+2