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* namespace YosysClifford Wolf2014-09-271-2/+10
* Fixed techmap_wrap for techmap_celltypeClifford Wolf2014-09-141-9/+16
* Added techmap_wrap attributeClifford Wolf2014-09-141-5/+28
* Added 'techmap_maccmap' techmap attributeClifford Wolf2014-09-071-19/+53
* Added "techmap -autoproc"Clifford Wolf2014-09-011-2/+18
* Only call proc_share_dirname() in techmap when necessaryClifford Wolf2014-08-231-2/+1
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-231-7/+6
* Renamed toposort.h to utils.hClifford Wolf2014-08-171-1/+1
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-151-3/+3
* document "techmap -map %<design-name>"Clifford Wolf2014-08-151-0/+3
* Implemented recursive techmapClifford Wolf2014-08-031-16/+62
* Implemented simplemap support for "techmap -extern"Clifford Wolf2014-08-021-5/+40
* Bugfix in "techmap -extern"Clifford Wolf2014-08-021-0/+1
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-021-1/+1
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-021-3/+5
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-18/+18
* Replaced sha1 implementationClifford Wolf2014-08-011-6/+1
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-1/+1
* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-311-2/+2
* Added "techmap -assert"Clifford Wolf2014-07-311-13/+42
* Added techmap CONSTMAP featureClifford Wolf2014-07-301-10/+119
* Added "techmap -map %{design-name}"Clifford Wolf2014-07-291-7/+16
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-4/+3
* Added techmap -externClifford Wolf2014-07-271-16/+64
* Added topological sorting to techmapClifford Wolf2014-07-271-20/+52
* Using new obj iterator API in a few placesClifford Wolf2014-07-271-10/+10
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-11/+11
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-5/+5
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-8/+8
* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-6/+4
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-1/+1
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-9/+9
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-9/+9
* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-261-8/+4
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-16/+21
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-231-8/+9
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-221-1/+1
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-9/+9
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-9/+9
* Added call_on_selection() and call_on_module() APIClifford Wolf2014-07-201-9/+1
* Added support for "blackbox" attribute to flatten/techmapClifford Wolf2014-07-171-1/+4
* be more verbose when techmap yielded processesJohann Glaser2014-05-261-1/+5
* Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-131-0/+1
* - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_shar...Siesh1oo2014-03-121-1/+2
* Added techmap -max_iter optionClifford Wolf2014-03-061-0/+10
* Added _TECHMAP_REPLACE_ feature to techmapClifford Wolf2014-02-201-4/+21
* Added techmap support for _TECHMAP_CONNMAP_*_Clifford Wolf2014-02-181-0/+39
* Better preserve wires when flattening (in comparison to techmap)Clifford Wolf2014-02-171-12/+12
* Added some additional checks to techmapClifford Wolf2014-02-161-0/+14
* Added CONSTMSK and CONSTVAL feature to techmapClifford Wolf2014-02-161-0/+23