| Commit message (Expand) | Author | Age | Files | Lines |
* | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 1 | -1/+1 |
* | Use C++11 final/override keywords. | whitequark | 2020-06-18 | 1 | -2/+2 |
* | Clean up `passes/techmap/hilomap.cc`. | Alberto Gonzalez | 2020-04-09 | 1 | -6/+2 |
* | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
* | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
* | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
* | Fixes in "hilomap" help message | Clifford Wolf | 2014-10-08 | 1 | -4/+2 |
* | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -0/+4 |
* | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -2/+2 |
* | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
* | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -2/+2 |
* | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -2/+2 |
* | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -2/+2 |
* | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -8/+2 |
* | Fixed all users of SigSpec::chunks_rw() and removed it | Clifford Wolf | 2014-07-23 | 1 | -14/+12 |
* | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created... | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
* | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
* | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
* | Replaced depricated NEW_WIRE macro with module->addWire() calls | Clifford Wolf | 2014-07-21 | 1 | -2/+2 |
* | Added hilomap command | Clifford Wolf | 2014-01-19 | 1 | -0/+129 |