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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:15:14 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:39:37 +0200 |
| commit | 4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 (patch) | |
| tree | 27801c4b0171a2491ff6817ebb6d2a1d1484c086 /passes/techmap/hilomap.cc | |
| parent | 16e5ae0b92ac4b7568cb11a769e612e152c0042e (diff) | |
| download | yosys-4b4048bc5feba1ab05c7a63f12c0a17879cb7e04.tar.gz yosys-4b4048bc5feba1ab05c7a63f12c0a17879cb7e04.tar.bz2 yosys-4b4048bc5feba1ab05c7a63f12c0a17879cb7e04.zip | |
SigSpec refactoring: using the accessor functions everywhere
Diffstat (limited to 'passes/techmap/hilomap.cc')
| -rw-r--r-- | passes/techmap/hilomap.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index 22f4c7d1d..ac41e47ca 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -31,7 +31,7 @@ static RTLIL::SigChunk last_hi, last_lo; void hilomap_worker(RTLIL::SigSpec &sig) { sig.expand(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) { if (!singleton_mode || last_hi.width == 0) { last_hi = RTLIL::SigChunk(module->addWire(NEW_ID)); |